AD7476ART Analog Devices, AD7476ART Datasheet - Page 2

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

S and B Versions: V
AD7476/AD7477/AD7478
AD7476–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
NOTES
1
2
3
4
Temperature ranges as follows: A, B Versions: –40°C to +85°C, S Version: –55°C to +125°C.
Operational from V
See Terminology.
Maximum B, S Versions specs apply as typical figures when V
Signal-to-Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Input Voltage Ranges
DC Leakage Current
Input Capacitance
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, I
Input Capacitance, C
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
V
I
Full Power-Down Mode
Power Dissipation
DD
DD
Second Order Terms
Third Order Terms
Normal Mode (Static)
Normal Mode (Operational)
Normal Mode (Operational)
Full Power-Down
3
3
DD
IN
IN
DD
= 2.0 V.
, SCLK Pin
, CS Pin
7
= 2.35 V to 5.25 V, f
3
IN
INL
INH
3, 5
OL
OH
3
3
3
3, 5
3
3
SCLK
3
= 12 MHz, f
A Version
69
70
70
–80
–82
–78
–78
10
30
6.5
12
± 1
± 0.75
± 0.5
± 0.5
0 to V
± 1
30
2.4
1.8
0.4
0.8
± 1
± 1
10
V
0.4
± 10
10
Straight (Natural) Binary
0.8
500
350
1000
2.35/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
3
DD
– 0.2
DD
DD
1, 2
= 5.25 V.
SAMPLE
1
(A Version: V
B Version
70
71
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
± 1.5
± 1.5
0 to V
± 1
30
2.4
1.8
0.4
0.8
± 1
± 1
10
V
0.4
± 10
10
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
DD
= 600 kSPS unless otherwise noted; T
– 0.2
DD
1, 2
DD
= 2.7 V to 5.25 V, f
S Version
69
70
70
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
± 2
± 2
0 to V
± 1
30
2.4
1.8
0.4
0.8
± 1
± 1
10
V
0.4
± 10
10
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
DD
5
6
7
Specifications subject to change without notice.
Sample tested at 25°C to ensure compliance.
A Version: f
See Power Versus Throughput Rate section.
– 0.2
DD
1, 2
SAMPLE
Unit
dB min
dB min
dB min
dB typ
dB typ
dB typ
dB typ
ns max
ps typ
MHz typ
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
V
µA max
pF typ
V min
V min
V max
V max
µA max
µA typ
pF max
V min
V max
µA max
pF max
µs max
ns max
ns max
kSPS max
V min/max
mA typ
mA typ
mA max
mA max
µA max
µA max
mW max
mW max
µW max
µW max
SCLK
MAX = 1 MSPS; B, S Versions: f
= 20 MHz, f
A
= T
Test Conditions/Comments
f
T
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
S, B Versions, V
A Version, V
Guaranteed No Missed Codes to 12 Bits
V
V
V
Typically 10 nA, V
I
I
Sixteen SCLK Cycles
Full-Scale Step Input
Sine Wave Input ≤100 kHz
See Serial Interface Section
Digital I/Ps = 0 V or V
V
V
V
V
SCLK Off
SCLK On
V
V
V
V
MIN
IN
SOURCE
SINK
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
A
= 100 kHz Sine Wave
to T
= 25°C
= 4.75 V to 5.25 V. SCLK On or Off
= 2.35 V to 3.6 V. SCLK On or Off
= 4.75 V to 5.25 V. f
= 2.35 V to 3.6 V. f
SAMPLE
= 2.35 V
= 3 V
= 5 V
= 5 V. f
= 3 V. f
= 5 V. SCLK Off
= 3 V. SCLK Off
= 200 µA
MAX
= 200 µA; V
, unless otherwise noted.)
= 1 MSPS unless otherwise noted;
SAMPLE
SAMPLE
DD
= (2.7 V to 3.6 V)
DD
IN
DD
= (2.35 V to 3.6 V)
= f
= f
SAMPLE
= 0 V or V
= 2.35 V to 5.25 V
DD
SAMPLE
SAMPLE
SAMPLE
SAMPLE
MAX = 600 kSPS.
MAX
MAX
= f
= f
DD
SAMPLE
SAMPLE
6
6
4
MAX
;
MAX
6
6