AD7476ART Analog Devices, AD7476ART Datasheet - Page 15

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

MICROPROCESSOR INTERFACING
The serial interface on the AD7476/AD7477/AD7478 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7476/AD7477/AD7478 with some of the more common
microcontroller and DSP serial interface protocols.
AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7476/
AD7477/AD7478. The CS input allows easy interfacing between
the TMS320C5x/C54x and the AD7476/AD7477/AD7478 with-
out any glue logic required. The serial port of the TMS320C5x/
C54x is set up to operate in burst mode with internal CLKX (Tx
serial clock) and FSX (Tx frame sync). The serial port control reg-
ister (SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1 and TXM = 1. The format bit, FO, may be set to 1 to
set the word length to eight bits, in order to implement the
power-down mode on the AD7476/AD7477/AD7478. The con-
nection diagram is shown in Figure 24. It should be noted that for
signal processing applications, it is imperative that the frame syn-
chronization signal from the TMS320C5x/C54x will provide
equidistant sampling.
AD7476/AD7477/AD7478 to ADSP-21xx Interface
The ADSP21xx family of DSPs are interfaced directly to the
AD7476/AD7477/AD7478 without any glue logic required. The
SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
AD7478*
AD7476/
AD7477/
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
CS
CLKX
CLKR
DR
FSX
FSR
TMS320C54x*
TMS320C5x/
To implement the power-down mode SLEN should be set to
1001 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 25. The ADSP-21xx has the TFS and RFS of
the SPORT tied together, with TFS set as an output and RFS
set as an input. The DSP operates in Alternate Framing Mode
and the SPORT control register is set up as described. The
frame synchronization signal generated on the TFS is tied to
CS and as with all signal processing applications equidistant
sampling is necessary. However, in this example, the timer inter-
rupt is used to control the sampling rate of the ADC and, under
certain conditions, equidistant sampling may not be achieved.
The timer registers etc., are loaded with a value that will provide
an interrupt at the required sample interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the reading
of data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given
(i.e., AX0 = TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone High, Low, and High before
transmission will start. If the timer and SCLK values are chosen
such that the instruction to transmit occurs on or near the rising
edge of SCLK, the data may be transmitted or it may wait until
the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
a SCLK of 2 MHz is obtained, and eight master clock periods
will elapse for every one SCLK period. If the timer registers
are loaded with the value 803, 100.5 SCLKs will occur between
interrupts and subsequently between transmit instructions. This
situation will result in nonequidistant sampling as the transmit
instruction is occurring on an SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, equidis-
tant sampling will be implemented by the DSP.
AD7478*
AD7476/
AD7477/
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
AD7476/AD7477/AD7478
CS
SCLK
DR
RFS
TFS
ADSP-21xx*