ADV7177 Analog Devices, ADV7177 Datasheet - Page 13

• Manufacturer Part Number: ADV7177
• Description: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
• Manufacturer: Analog Devices

COLOR BAR GENERATION
The ADV7177/ADV7178 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
SQUARE PIXEL MODE
The ADV7177/ADV7178 can be used to operate in square pixel
mode. For NTSC operation an input clock of 24.5454 MHz is
required. Alternatively an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
PIXEL TIMING DESCRIPTION
The ADV7177/ADV7178 can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
REV. 0
–10
–20
–30
–40
–50
–60
0
0
2
Figure 13. PAL UV Filter
4
FREQUENCY – MHz
6
8
10
12
–13–
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
OSD
The ADV7177 supports OSD. There are twelve 8-bit OSD
registers, loaded with data from the four most significant bits of
Y, Cb, Cr input pixel data bytes. A choice of eight colors can,
therefore, be selected via the OSD_0, OSD_1, OSD_2 pins,
each color being a combination of 12 bits of Y, Cb, Cr pixel
data. The display is under control of the OSD_EN pin. The
OSD window can be an entire screen or just one pixel, its size
may change by using the OSD_EN signal to control the width on a
line-by-line basis. Figure 4 illustrates OSD timing on the ADV7177.
SUBCARRIER RESET
The ADV7177/ADV7178 can be used in subcarrier reset
mode. The subcarrier will reset to Field 0 at the start of the
following field when a low to high transition occurs on this
input pin.
VIDEO TIMING DESCRIPTION
The ADV7177/ADV7178 is intended to interface to off-
the-shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7177/ADV7178 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7177/ADV7178 generates all of the re-
quired horizontal and vertical timing periods and levels for the
analog video outputs.
The ADV7177/ADV7178 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
In addition, the ADV7177/ADV7178 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
The ADV7177/ADV7178 has four distinct master and four
distinct slave timing configurations. Timing Control is estab-
lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
ADV7177/ADV7178