ADV7177 Analog Devices, ADV7177 Datasheet - Page 23

• Manufacturer Part Number: ADV7177
• Description: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
• Manufacturer: Analog Devices

Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
REV. 0
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
•
•
SR7
ZERO SHOULD BE WRITTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
0
TO THESE BITS
SR7–SR6 (00)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
0
SR6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
BE WRITTEN TO
ZERO SHOULD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
1
SR5
THIS BIT
MR07
(0)
ADV7178 SUBADDRESS REGISTER
MODE REGISTER 0
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
MACROVISION REGISTER
MACROVISION REGISTER
MR06
0
1
"
"
OUTPUT SELECT
MR07
SR4
YC OUTPUT
RGB/YUV OUTPUT
"
"
MR06
SR3
MR05
Figure 32. Mode Register 0 (MR0)
0
1
Figure 31. Subaddress Register
RGB SYNC
DISABLE
ENABLE
MR05
SR2
MR04 MR03
0
0
1
1
0
1
0
1
MR04
FILTER SELECT
–23–
SR1
LOW-PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW-PASS FILTER (B)
MR0 BIT DESCRIPTION
Encode Mode Control (MR01–MR00)
These bits are used to set up the encode mode. The ADV7177/
ADV7178 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7177/ADV7178 is configured in PAL mode.
Luminance Filter Control (MR04–MR03)
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03
and MR04 select one of four NTSC luminance filters. The
filters are illustrated in Figures 7 to 13.
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
0
MR03
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
1
SR0
MR02
PEDESTAL CONTROL
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
1
MR02
PEDESTAL OFF
PEDESTAL ON
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
ADV7177 SUBADDRESS REGISTER
MR01 MR00
0
0
1
1
STANDARD SELECTION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
0
MR01
OUTPUT VIDEO
0
1
0
1
MODE REGISTER 0
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
OSD REGISTER
"
"
OSD REGISTER
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
ADV7177/ADV7178
MR00
"
"