ADV7191 Analog Devices, ADV7191 Datasheet - Page 21

• Manufacturer Part Number: ADV7191
• Description: Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
• Manufacturer: Analog Devices

Mode 0 (CCIR–656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7190/ADV7191 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel
Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 33. The
BLANK pins (if not used) should be tied high during this mode.
RTC
NOTES:
1
2
3
NTSC/PAL M SYSTEM
F
SEQUENCE BIT
RESET BIT
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY
REGISTERS OF THE ADV7190/ADV7191.
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET ADV7190/ADV7191’s DDS
SC
H/L TRANSITION
(525 LlNES/60Hz)
(625 LINES/50Hz)
COUNT START
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7190 FSC DDS REGISTER IS F
INPUT PIXELS
TIME SLOT: 01
PAL SYSTEM
COMPOSITE
OR CABLE
128
e.g., VCR
ANALOG
VIDEO
VIDEO
LOW
13
Y
END OF ACTIVE
RESERVED
VIDEO LINE
C
DECODER
ADV7185
14 BITS
NOT USED IN
r Y
VIDEO
ADV7190
F
F
4 CLOCK
4 CLOCK
EAV CODE
0
0
DECODER
0
0
LCC1
14
MPEG
0
RESERVED
X
Y
4 BITS
P19–P12
8
0
1
0
19
GLL
21
8
0
1
0
M
U
X
ANCILLARY DATA
0
0
268 CLOCK
280 CLOCK
F
F
(HANC)
F
F
HSYNC
CLOCK
SCRESET/RTC/TR
P7–P0
VSYNC
A
B
SAMPLE
F
VALID
SC
A
B
PLL INCREMENT
A
B
SAMPLE
INVALID
ADV7190/ADV7191
8
0
1
0
8
0
GREEN/COMPOSITE/Y
GREEN/COMPOSITE/Y
1
0
SAV CODE
1
SC
4 CLOCK
F
F
4 CLOCK
START OF ACTIVE
RED/CHROMA/V
RED/CHROMA/V
PLL INCREMENTS BITS 21:0
0
0
BLUE/LUMA/U
BLUE/LUMA/U
VIDEO LINE
0
0
LOCKED CLOCK
X
Y
C
b Y
8/LINE
ADV7190/ADV7191
1440 CLOCK
1440 CLOCK
RESERVED
C
r
5 BITS
Y
HSYNC
0
C
b
SEQUENCE
Y
BIT
C
r
2
67 68
Y
RESET
C
b
, VSYNC and
BIT
3
RESERVED