ADV7191 Analog Devices, ADV7191 Datasheet - Page 7

• Manufacturer Part Number: ADV7191
• Description: Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
• Manufacturer: Analog Devices

3.3 V TIMING CHARACTERISTICS
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL
TELETEXT PORT
RESET CONTROL
PLL
NOTES
1
2
3
4
Specifications subject to change without notice.
Temperature range T
Guaranteed by characterization.
Pixel Port consists of:
Data: P15–P0 Pixel Inputs,
Control: HSYNC, VSYNC, BLANK,
Clock: CLKIN Input.
Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
Analog Output Delay
DAC Analog Output Skew
PORT
Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t
RESET Low Time
PLL Output Frequency
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t
Pipeline Delay, t
CLOCK
3
MIN
15
15
4
18
to T
5
17
(2× Oversampling)
(4× Oversampling)
12
10
11
9
MAX
12
11
: 0°C to 70°C.
2
1
16
14
3
8
4
7
13
6
Min
0
0.6
1.3
0.6
0.6
100
0.6
8
8
6
4
2.5
3
(V
specifications T
Typ
2
8
0.1
27
13
12
57
67
11
3
6
3
54
AA
= 3.3 V
Max
400
300
300
20
150 mV, V
MIN
to T
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
ns
ns
ns
ns
MHz
MAX
REF
1
unless otherwise noted
= 1.235 V, R
Test Conditions
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
SET1,2
= 1200
2
.)
ADV7190/ADV7191
unless otherwise noted. All