ADV7191 Analog Devices, ADV7191 Datasheet - Page 35

• Manufacturer Part Number: ADV7191
• Description: Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs
• Manufacturer: Analog Devices

TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)
Figure 60 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7190/ADV7191 is in master or
slave mode.
Timing Mode Selection (TR01–TR02)
These bits control the timing mode of the ADV7190/ADV7191.
These modes are described in more detail in the Video Tim-
ing Description and RESET Sequence sections of the data sheet.
BLANK Input Control (TR03)
This bit controls whether the BLANK input is used to accept
blank signals or whether blank signals are internally generated.
Note: When this input pin is tied high (to 5 V), the input is dis-
abled regardless of the register setting. It, therefore, should be
tied low (to Ground) to allow control over the I
Luma Delay (TR04–TR05)
The luma signal can be delayed by up to 222 ns (or six clock
cycles at 27 MHz) using TR04–TR05. For further information
see Chroma/Luma Delay section.
Min Luminance Value (TR06)
This bit is used to control the minimum luma output value
by the ADV7190/ADV7191 in 2× Oversampling Mode (MR 16 =
0). When this bit is set to a Logic 1, the luma is limited to 7.5IRE
below the blank level. When this bit is set to (0), the luma value
can be as low as the sync bottom level (40IRE below blanking).
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset, or changing to a new timing mode.
TR07
REGISTER RESET
MIN LUMINANCE VALUE
TIMING
TR06
TR07
0
1
LUMA MIN =
SYNC BOTTOM
LUMA MIN =
BLANK –7.5 IRE
TR06
2
C register.
TR05
TR05 TR04
0
0
1
1
LUMA DELAY
0
1
0
1
TR04
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TR03
0
1
BLANK INPUT
CONTROL
TIMING REGISTER 1
(TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is an 8-bit-wide register.
Figure 61 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR10–TR11)
These bits adjust the HSYNC pulsewidth.
T
HSYNC to VSYNC Delay Control (TR12–TR13)
These bits adjust the position of the HSYNC output relative to
the VSYNC output.
T
HSYNC to VSYNC Rising Edge Control (TR14–TR15)
When the ADV7190/ADV7191 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the VSYNC
output rising edge.
T
VSYNC Width (TR14–TR15)
When the ADV7190/ADV7191 is configured in Timing Mode
2, these bits adjust the VSYNC pulsewidth.
T
HSYNC to Pixel Data Adjust (TR16–TR17)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master and slave timing
modes.
T
TR03
ENABLE
DISABLE
PCLK
PCLK
PCLK
PCLK
PCLK
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
TR02 TR01
0
0
1
1
TR02
TIMING MODE
CONTROL
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
TR01
TR00
0
1
MASTER / SLAVE
CONTROL
SLAVE TIMING
MASTER TIMING
TR00
ADV7190/ADV7191