SAA7390GP Philips Semiconductors, SAA7390GP Datasheet - Page 40

• Manufacturer Part Number: SAA7390GP
• Description: High performance Compact Disc-Recordable CD-R controller
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 57 Ending frame number: 0xF0F2, F0F3
11.5
The following bandwidth limitation must be observed in normal operation:
Table 58 Selection/test mode: 0xF0FE; note 1
Note
1. DRAMSEL1 and DRAMSEL0 are used to select the type of DRAM which is connected to the SAA7390. The test
Table 59 DRAMSEL field descriptions
1996 Jul 02
RES_TEST0
RES_TEST1
RES_TEST2
MNEMONIC
DRAMSEL1
DRAMSEL0
MNEMONIC
Only 833 ns is available between each data write from the front-end at the maximum 8 times transfer rate. At the end
of the frame, multiple front-end writes may stack up, so the microcontroller accesses to DRAM will be off
(PCLK stopped) during the end of frame time.
After power-up or reset, the register DRAMSEL should be programmed first.
DRAMSEL
High performance Compact
Disc-Recordable (CD-R) controller
LSTFHOST
LSTFHOST
REFRATE
modes are also defined by the DRAMSEL register.
FIELD
TEST
Miscellaneous buffer manager considerations
LOGIC
R/W
R/W
R/W
R/W
R/W
00
01
10
11
0
1
TEST
256 kbytes
1 Mbyte
not applicable
4 Mbytes
normal refresh rate
double refresh rate; set HIGH if clock is running at
reserved for test; setting this HIGH enables the DRAM access test, a write to INTRMSK sets
a front-end access test, and a write to PAGEREG sets a test ECC access
reserved for test; setting this HIGH enables the switch multiplexer control
reserved for test; setting this HIGH enables the interrupt test, a write to PAGEREG will set
interrupts
test mode; this bit must be set to enable the test modes, also, read back of any of the test
bits is gated by this bit
FRAME7
7
7
RES_TEST2 to RES_TEST0
FRAME6
6
6
FRAME5
5
5
40
FRAME4
4
DESCRIPTION
DATA BYTE
4
DATA BYTE
REFRATE DRAMSEL1 DRAMSEL0
FRAME3
3
1
3
2
normal rate, or 16.9 MHz
FRAME2
2
2
FRAME10 to FRAME8
Preliminary specification
FRAME1
1
1
SAA7390
FRAME0
0
0