SAA7390GP Philips Semiconductors, SAA7390GP Datasheet - Page 57
SAA7390GP
Manufacturer Part Number
SAA7390GP
Description
High performance Compact Disc-Recordable CD-R controller
Manufacturer
Philips Semiconductors
Datasheet
1.SAA7390GP.pdf
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Philips Semiconductors
15.6
The control communication between the CD-R engine and
the interface module is based on data blocks that are
swapped in the same cycle.
The control communication channel is byte and message
synchronous. Byte synchronization is realized with an
acknowledge after each byte that is transferred. Message
synchronization is ensured through resetting the serial
shift register after each communication synchronization
pulse. This is to detect the start of the next data block even
if a time-out or bit-slip occurs.
This control interface is used for the exchange of:
Table 78 SPI timing parameters
1996 Jul 02
handbook, full pagewidth
T
t
t
t
t
t
CH
CL
su
h
d
SYMBOL
cy
Sub-code data
Commands with parameters
Status information.
High performance Compact
Disc-Recordable (CD-R) controller
SPI interface timing
engine data available
user data available
serial clock cycle time
serial clock HIGH time
Serial clock LOW time
serial input data set-up time to COM_CLK
serial input data hold time from COM_CLK
serial output delay after COM_CLK
COMM_SYNC
COM_ACK
COM_CLK
Fig.21 Serial communication timing and synchronization.
PARAMETER
57
The control interface channel is implemented as a
bidirectional, synchronous, high-speed serial link, having
the following advantages:
The Q sub-code and header data can be coupled
(synchronized)
The user part has real time access of the Q sub-code
information
The user part has full control over the CD-R engines
mode of operation, for example synchronous stop while
recording
High speed data transfers are possible; up to 2 Mbits/s
for the microcontroller in slave mode.
500
210
210
80
80
0
MIN.
Preliminary specification
150
MAX.
SAA7390
MGE523
ns
ns
ns
ns
ns
ns
UNIT
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