SAA7390GP Philips Semiconductors, SAA7390GP Datasheet - Page 41

• Manufacturer Part Number: SAA7390GP
• Description: High performance Compact Disc-Recordable CD-R controller
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 60 Automatic start and stop control functions (same address): 0xF0C5, F0C6 and F0C7
The multiplexing between the start and stop registers is
achieved by programming STOP in BMFECTL. If STOP is
clear then STRTMIN, STRTSEC and STRTFRM are
accessible, otherwise STOPCNT may be accessed.
These registers contain the start address (MSF) and the
stop count for the automatic read control function. When
the block decoders header or registers equal the start
address, the front-end will start to send data to the buffer
manager until the down counter STOPCNT decrements to
zero, at which time the data flow stops.
The header registers are selected then AUDMODE in
FECTL is LOW, otherwise the Q registers are selected;
the latter event is used for loading audio data. The start
registers are selected when FEWBLK in BMFECLT is
LOW, otherwise the STOPCNT registers are selected. The
start registers should be programmed to ‘Header 1’. If
EFAB (C2 failure) is asserted while the header is shifting
in, the data flow will not start. The same is true for BADQ
(Q channel CRC failure) used in the audio mode.
11.6
The SAA7390 provides a 16 address wide pass through
mechanism to communicate to an external SCSI or ATAPI
interface device. Supported devices include the 53CF9X
series of SCSI controllers and the Wapiti ATAPI controller.
The register definitions for the external device can be
found in the corresponding data sheet.
1996 Jul 02
MNEMONIC
STRTFRM
STOPCNT
STOPCNT
STRTSEC
High performance Compact
Disc-Recordable (CD-R) controller
STRTMIN
Host interface related registers
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
41
SECOND7 to SECOND0
MINUTE7 to MINUTE0
COUNT7 to COUNT0
FRAME7 to FRAME0
In the 53CF9X series of SCSI controllers, some registers
are read only and others are write only. These share the
same address and the multiplexing between the two
depends on the read or write select.
The address mapping is: 0xF0A4 to 0xF0A7,
0xF0AC to 0xF0AF, 0xF0B4 to 0xF0B7,
0xF0BC to 0xF0BF maps onto the external interface
device address range 0x00 to 0x0F respectively.
11.7
This section outlines the registers which are related to the
modified CDB2 block encoder. Figure 13 shows a
functional block diagram for the CDB2.
Figure 14 explains the generation of header and
sub-header information.
4
DATA BYTE
CDB2 related registers
3
2
COUNT10 to COUNT8
Preliminary specification
1
SAA7390
0