MC68020 Motorola, MC68020 Datasheet - Page 67
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MC68020
Manufacturer Part Number
MC68020
Description
(MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
Manufacturer
Motorola
Datasheet
1.MC68020.pdf
(306 pages)
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5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
The combination of operand size, operand alignment, and port size determine the number
of bus cycles required to perform a particular memory access. Table 5-6 lists the number
of bus cycles required for different operand sizes to different port sizes with all possible
alignment conditions for read/write cycles.
Table 5-6 reveals that bus cycle throughput is significantly affected by port size and
alignment. The MC68020/EC020 system designer and programmer should be aware of
and account for these effects, particularly in time-critical applications.
5-20
31
D31
OP0
MSB
OP1
XXX
*
Instruction prefetches are always two words from a long-word boundary
Instruction
Byte Operand
Word Operand
Long-Word Operand
Figure 5-17. Misaligned Long-Word Operand Read
LONG-WORD OPERAND (REGISTER)
Operand Size
OP1
UMB
OP2
Table 5-6. Memory Alignment and Port Size
XXX
LONG-WORD MEMORY
*
Influence on Read/Write Bus Cycles
DATA BUS
from Long-Word Port Example
M68020 USER’S MANUAL
LMB
XXX
OP3
OP2
1:2:4
1:1:2
1:2:4
1:1:1
(Data Port Size = 32 Bits:16 Bits:8 Bits)
00
Number of Bus Cycles
OP0
LSB
XXX
OP3
1:1:1
1:2:2
2:3:4
N/A
01
A1, A0
D0
0
SIZ1 SIZ0 A2
0
1
1:1:1
1:1:2
2:2:4
N/A
10
MC68020/EC020
0
1
0
1
A1
1:1:1
2:2:2
2:3:4
1
0
N/A
11
A0
1
0
MEMORY CONTROL
DSACK1
L
L
MOTOROLA
DSACK0
L
L
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