MC68HC58 Motorola, MC68HC58 Datasheet - Page 14

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

The logic section of the DLC consists of the MCU interface, transmit and receive bit
timing logic, transmit and receive FIFO buffer logic, the control and timing block (fram-
ing, error detection and bus arbitration), and command and status control logic.
The bus transceiver allows the DLC to be directly connected to the J1850 bus, thus
providing a complete link between the MCU application and the J1850 bus.
Transceiver operation is constrained by available power and the need to function reli-
ably in the presence of conducted and induced noise. The main source of conducted
noise is the ground offset between nodes. The DLC operates correctly under any com-
bination of offsets up to a maximum differential of two volts at any frequency. Induced
noise tends to be composed of short-duration pulses. The receive bit timing section
includes a digital filter to remove these pulses.
The transceiver provides a waveshaped seven volt serial analog signal in response to
a timed signal from the bit timing logic. The transceiver also receives J1850 bus wave-
forms, and provides the control logic with unfiltered inputs.
To achieve the 7-volt signal level necessary for the J1850 bus, the transceiver has a
separate 9- to 16-volt power supply input (V
. The transceiver actively drives the
)
BATT
J1850 bus high, and passively allows an RC load to pull the J1850 bus down. If ground
is lost, the transceiver releases the J1850 bus. The transceiver also protects the MCU
interface by not passing on any disruptive signals that may be on the J1850 bus.
MOTOROLA
INTRODUCTION
MC68HC58
1-2
TECHNICAL DATA