MC68HC58 Motorola, MC68HC58 Datasheet - Page 66

• Manufacturer Part Number: MC68HC58
• Description: Data Link Controller
• Manufacturer: Motorola

4-22
MOTOROLA
The IFR bit in the completion code byte indicates whether the associated frame in the
RxFIFO buffer is an IFR. When an IFR has been sent, the RxFIFO buffer contains the
initial frame, with completion code, plus the IFR and its completion code. The host
MCU must check the completion codes to determine that an IFR has been received.
An IFR starts with a normalization (NB) bit. This bit signals whether the IFR was
queued by a “send IFR on EOD without CRC” command (NB = 0), or by a “send IFR
on EOD with CRC command” (NB = 1). The “in-frame response” command (IFRC) bit
in the completion code byte also indicates whether a CRC byte is appended to the IFR.
The host MCU must monitor the IFRC if error checking is to be used. Due to zero-dom-
inance, J1850 bus arbitration between an IFR without CRC and an IFR with CRC is
won by an IFR without CRC.
Table 4-4 shows IFR error conditions. When errors are detected during an IFR, the
IFR is terminated. A completion code indicating that the frame was an IFR and that an
error occurred is placed in the RxFIFO buffer.
Error in frame requiring response
J1850 bus idle when IFR loaded
Error in IFR during transmission
IFR loaded without first byte
TxFIFO buffer underrun
IFR command, no data
IFR loaded after EOD
IFR loses arbitration
Condition
A DLC cannot transmit an IFR to a message it is transmitting.
DATA LINK CONTROLLER OPERATION
Table 4-4 IFR Error Conditions
Transmission halts, transmitter reset, TxFIFO buffer flushed
Transmission halts, TxFIFO buffer flushed (no IFR sent)
Transmitter reset, TxFIFO buffer flushed (no IFR sent)
Transmitter reset, TxFIFO buffer flushed
Transmitter reset, TxFIFO buffer flushed
Transmitter reset, TxFIFO buffer flushed
Transmitter reset, TxFIFO buffer flushed
CRC complemented on truncated IFR
NOTE
Action Taken
TECHNICAL DATA
MC68HC58