LTC6802IG-2 LINER [Linear Technology], LTC6802IG-2 Datasheet - Page 14

• Manufacturer Part Number: LTC6802IG-2
• Description: Multicell Addressable Battery Stack Monitor
• Manufacturer: LINER [Linear Technology]

LTC6802-2
applicaTions inForMaTion
USING THE LTC6802-2 WITH LESS THAN 12 CELLS
The LTC6802-2 can typically be used with as few as 4 cells.
The minimum number of cells is governed by the supply
voltage requirements of the LTC6802-2. The sum of the
cell voltages must be 10V to guarantee that all electrical
specifications are met.
Figure 5 shows an example of the LTC6802-2 when used to
monitor 7 cells. The lowest C inputs connect to the 7 cells
and the upper C inputs connect to V
tions, e.g., 9 cells, would be configured in the same way:
the lowest C inputs connected to the battery cells and the
unused C inputs connected to V
result in a reading of 0V for those channels.
The ADC can also be commanded to measure a stack of
cells by making 10 or 12 measurements, depending on the
state of the CELL10 bit in the control register. Data from all
10 or 12 measurements must be downloaded when read-
ing the conversion results. The ADC can be commanded
to measure any individual cell voltage.

Figure 5. Monitoring 7 Cells with the LTC6802-2
NEXT HIGHER GROUP OF 7 CELLS
NEXT LOWER GROUP OF 7 CELLS
+
+
+
+
+
+
+
+
. The unused inputs will
V
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
V
+
−
+
LTC6802-2
. Other configura-
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USING THE GENERAL PURPOSE INPUTS/OUTPUTS
(GPIO1, GPIO2)
The LTC6802-2 has two general purpose digital inputs/out-
puts. By writing a GPIO configuration register bit to a logic
low, the open-drain output can be activated. The GPIOs
give the user the ability to turn on/off circuitry around the
LTC6802-2. One example might be a circuit to verify the
operation of the system.
When a GPIO configuration bit is written to a logic high,
the corresponding GPIO pin may be used as an input.
The read back value of that bit will be the logic level that
appears at the GPIO pin.
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See the Monitor Mode section.
WATCHDOG TIMER CIRCUIT
The LTC6802-2 includes a watchdog timer circuit. If no
activity is detected on the SCKI pin for 2.5 seconds, the
WDTB open-drain output is asserted low. The WDTB pin
remains low until an edge is detected on the SCKI pin.
When the watchdog timer circuit times out, the configura-
tion bits are reset to their default (power-up) state.
In the power-up state, the S outputs are off. Therefore, the
watchdog timer provides a means to turn off cell discharg-
ing should communications to the MPU be interrupted.
The IC is in the minimum power standby mode after a
time out. Note that externally pulling the WDTB pin low
will not reset the configuration bits.
The watchdog timer operation is disabled when MMB
is low.
When reading the configuration register, byte CFG0 bit 7
will reflect the state of the WDTB pin.
REVISION CODE
The temperature register group contains a 3-bit revision
code. If software detection of device revision is neces-
sary, then contact the factory for details. Otherwise, the
code can be ignored. In all cases, however, the values of
all bits must be used when calculating the packet error
code (PEC) CRC byte on data reads.
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