LTC6802IG-2 LINER [Linear Technology], LTC6802IG-2 Datasheet - Page 9

• Manufacturer Part Number: LTC6802IG-2
• Description: Multicell Addressable Battery Stack Monitor
• Manufacturer: LINER [Linear Technology]

pin FuncTions
pin becomes high impedance. Either a “1” or a “0” is read
back, depending on the voltage present at Pin 35. The
GPIOs make it possible to turn on/off circuitry around
the LTC6802-2, or read logic values from a circuit around
the LTC6802-2.
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See Monitor Mode in the Applications
Information section.
A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs.
These pins are tied to V
pins (V
See LTC6802-2 Address Commands in the Serial Port
subsection of the Applications Information section.
block DiagraM
REG
= 1, V
–
= 0) determines the LTC6802-2 address.
21
22
23
24
25
26
27
2
3
4
REG
C12
S12
C11
S3
C2
S2
C1
S1
V
NC
–
or V
10k
10k
10k
10k
10
–
. The state of the address
TEMP
DIE
28
MUX
V
TEMP1
29
EXTERNAL
TEMP
V
TEMP2
30
V
REF
∆∑ A/D CONVERTER
SCKI (Pin 41): Serial Clock Input. The SCKI pin inter-
faces to any logic gate (TTL levels). See Serial Port in the
Applications Information section.
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
any logic gate (TTL levels). See Serial Port in the Applica-
tions Information section.
SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS
open drain output and requires an external resistor pull-up.
See Serial Port in the Applications Information section.
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
pin interfaces to any logic gate (TTL levels). See Serial
Port in the Applications Information section.
REFERENCE
12
COMMUNICATIONS
REGULATOR
WATCHDOG
REGISTER
CONTROL
RESULTS
TIMER
AND
1
V
+
GPIO2
GPIO1
WDTB
MMB
V
CSBI
SCKI
SDO
TOS
REG
SDI
68022 BD
A3
A2
A1
A0
31
34
40
39
38
37
44
43
42
41
36
35
33
32
LTC6802-2
68022fa