LTC6802IG-2 LINER [Linear Technology], LTC6802IG-2 Datasheet - Page 28

• Manufacturer Part Number: LTC6802IG-2
• Description: Multicell Addressable Battery Stack Monitor
• Manufacturer: LINER [Linear Technology]

applicaTions inForMaTion
LTC6802-2
ADDING CALIBRATION AND
FULL-STACK MEASUREMENTS
By adding multiplexing hardware, additional signals can
be digitized by the CELL1 ADC channel. One useful signal
to provide is a high accuracy voltage reference, such as
from an LT
ings of this signal, host software can provide correction
of the LTC6802-2 readings to improve the accuracy over
that of the internal LTC6802-2 reference, and/or validate
ADC operation. Another useful signal is a measure of the

Figure 14. Using Diode Sensors as Hot-Spot Detectors
®
1461A-4 or LTC6652A-4.096. By periodic read-
LTC6802-2
Figure 15. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port
CELL12
CELL1
V
V
TEMP2
TEMP1
V
V
REG
REF
NC
V
−
100
LTC6802-2
TP0610K
200k
GPIO2
GPIO1
WDTB
V
200k
TP0610K
REG
C1
V
−
0 = REF_EN
0 = CELL1
68022 F14
1M
1µF
100nF
150
2N7002
1M
68022 F15
2.2M
2N7002
1M
TP0610K
TP0610K
total stack potential. This provides a redundant operational
measurement of the cells in the event of a malfunction in
the normal acquisition process, or as a faster means of
monitoring the entire stack potential. Figure 15 shows
a means of providing both of these features. A resistor
divider is used to provide a low voltage representation of
the full stack potential (C12 to C0 voltage) with MOSFETs
that decouple the divider current under unneeded condi-
tions. Other MOSFETs, in conjunction with an op amp
having a shutdown mode, form a voltage selector that
allows measurement of the normal cell1 potential (when
GPIO1 is low) or a buffered MUX signal. When the MUX
is active (GPIO1 is high), selection can be made between
the reference (4.096V) or the full-stack voltage divider
(GPOI2 set low will select the reference). During idle time
when the LTC6802-2 WDTB signal goes low, the external
circuitry goes into a power-down condition, reducing
battery drain to a minimum. When not actively perform-
ing measurements, GPIO1 should be set low and GPIO2
should be set high to achieve the lowest power state for
the configuration shown.
10M
1M
90.9k
V
STACK12
SD
LT1636
+
–
DNC
V
SD
GND
LT1461A-4
IN
1M
V
DNC
DNC
DNC
OUT
2.2µF
COM
V
4.096V
DD
TC4W53FU
CH0
INH
CH1
V
EE
SEL
V
SS
68022fa