LTC695-3.3 LINER [Linear Technology], LTC695-3.3 Datasheet - Page 10

• Manufacturer Part Number: LTC695-3.3
• Description: 3.3V Microprocessor Supervisory Circuits
• Manufacturer: LINER [Linear Technology]

LTC694-3.3/LTC695-3.3
A
10
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
V
V
V
BATT ON
PFI
PFO
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
CC
OUT
BATT
PPLICATI
Figure 4. 10 /0.1 F Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the V
While the Battery is Removed, Eliminating Spurious Resets
STATUS
C2 monitors V
V
The supply current is 1 A maximum.
Logic high. The open-circuit output voltage is equal to V
Power failure input is ignored
Logic low
Logic low
Logic high. The open-circuit output voltage is equal to V
Watchdog input is ignored.
Logic high. The open-circuit output voltage is equal to V
Chip Enable input is ignored.
Logic high. The open-circuit output voltage is equal to V
OSC IN is ignored
OSC SEL is ignored
OUT
is connected to V
10
CE OUT
O
CE IN
V
CC
U
V
CC
OUT
S
for active switchover
2.7M
= V
BATT
I FOR ATIO
U
BATT
through an internal PMOS switch
0.1 F
BATT
W
Figure 5. Timing Diagram for CE IN and CE OUT
Pin to Ground
V
BATT
LTC694-3.3
LTC695-3.3
GND
694/5-3.3 F04
U
V1
OUT
OUT
OUT
OUT
V2
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
Memory Protection
The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by
preventing write operations when V
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When V
CE OUT follows CE IN with a typical propagation delay of
30ns. When V
V
OUT is an alternative signal to drive the CE, CS, or Write
input of battery backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
Memory protection can also be achieved with the LTC694-
3.3 by using RESET as shown in Figure 7.
Power-Fail Warning
The LTC694-3.3/LTC695-3.3 generate a Power Failure
Output (PFO) for early warning of failure in the
microprocessor’s power supply. This is accomplished by
BATT
BATT
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
, CE OUT is forced high, independent of CE IN. CE
to GND and V
RESET THRESHOLD HYSTERESIS
CC
falls below the reset voltage threshold or
OUT
to V
CC
.
V
OUT
694/5-3.3 F05
CC
= V
BATT
is at invalid level.
CC
is 3.3V,