LTC695-3.3 LINER [Linear Technology], LTC695-3.3 Datasheet - Page 12

• Manufacturer Part Number: LTC695-3.3
• Description: 3.3V Microprocessor Supervisory Circuits
• Manufacturer: LINER [Linear Technology]

LTC694-3.3/LTC695-3.3
A
Choose R3 = 200k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
R2 = 15.8k, Choose nearest 5% resistor 16k and recalcu-
late V
The 15.6ms allows enough time to execute shutdown
procedure for microprocessor and 810mV of hysteresis
would prevent PFO from going low due to the noise of V
Example 2: The circuit in Figure 9 can be used to measure
the regulated 3.3V supply to provide early warning of
power failure. Because of variations in the PFI threshold,
this circuit requires adjustment to ensure the PFI com-
parator trips before the reset threshold is reached. Adjust
R5 such that the PFO output goes low when the V
reaches the desired level (e.g., 3.1V).
Monitoring the Status of the Battery
C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
12
PPLICATI
R3 3.88 R1
V
V
5V =1.3V 1+
V
V
(4.96V – 3.4V)
HYSTERESIS
HYSTERESIS
L
H
100mV/ms
L
,
1.3V 1
1.3V 1
= 5.77V – 4.96V = 810mV
O
51
51
16k
16 k
R2
51k
3 V
U
.3
k
k
15.6ms
S
–
–
R3
R1
(3.3V – 1.3V)51
(3.3V – 1.3V)51
2 00k
I FOR ATIO
51k
U
1 3 210
1.3V(210k
.
850mV
V
(
5
.
W
77
k
)
)
V
k
k
4 96
CC
U
.
supply
V
IN
.
Watchdog Timer
The LTC694-3.3/LTC695-3.3 provide a watchdog timer
function to monitor the activity of the microprocessor. If
the microprocessor does not toggle the watchdog input
(WDI) within a seleced time-out period, RESET is forced to
active low for a minimum of 140ms. The reset active time
is adjustable on the LTC695-3.3. Since many systems can
not service the watchdog timer immediately after a reset,
the LTC695-3.3 has a longer time-out period (1.0 second
minimum) right after a reset is issued. The normal time-
out period (70ms minimum) becomes effective following
the first transition of WDI after RESET is inactive. The
watchdog time-out period is fixed at 1.0 second minimum
on the LTC694-3.3. Figure 11 shows the timing diagram of
watchdog time-out period and reset active time. The
watchdog time-out period is restarted as soon as RESET
is inactive. When either a high-to-low or low-to-high
transition occurs at the WDI pin prior to time-out, the
watchdog time is reset and begins to time out again. To
ensure the watchdog time does not time out, either a high-
to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum time-out period. If the
input to the WDI pin remains either high or low, reset
pulses will be issued every 1.6 seconds typically. The
watchdog time can be deactivated by floating the WDI pin.
The timer is also disabled when V
voltage threshold or V
Figure 10. Back-Up Battery Monitor with Optional Test Load
2.4V
OPTIONAL TEST LOAD
R1
1M
R2
1.6M
20k
R
L
V
PFI
BATT
CE OUT
BATT
LTC695-3.3
3.3V
.
V
CC
GND
CE IN
PFO
CC
falls below the reset
LOW-BATTERY SIGNAL
TO P I/O PIN
I/O PIN
694/5-3.3 F10