LTC695-3.3 LINER [Linear Technology], LTC695-3.3 Datasheet - Page 6

• Manufacturer Part Number: LTC695-3.3
• Description: 3.3V Microprocessor Supervisory Circuits
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
LTC694-3.3/LTC695-3.3
V
with a 0.1 F capacitor.
V
a capacitor of 0.1 F or greater. During normal operation,
V
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5 . When V
is internally switched to V
used, connect V
V
auxiliary power connected to V
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, V
GND: Ground Pin.
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when V
V
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
high when V
PFI: Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or V
C3 is not used.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V
PFO is forced low.
RESET: Logic Output for P Reset Control. Whenever V
falls below either the reset voltage threshold (2.90V,
typically) or V
returns to 3.3V, the reset pulse generator forces RESET to
remain active low for a minimum of 140ms. When the
watchdog timer is enabled but not serviced prior to a
preset time-out period, the reset pulse generator also
forces RESET to active low for a minimum of 140ms for
6
CC
OUT
OUT
BATT
CC
U
: 3.3V Supply Input. The V
. The output typically sinks 25mA and can provide base
: Voltage Output for Backed Up Memory. Bypass with
obtains power from V
: Back-Up Battery Input. When V
U
OUT
CC
BATT
OUT
is lower than V
is internally switched to V
, RESET goes active low. After V
to V
BATT
U
CC
should be connected to GND.
BATT
.
OUT
CC
CC
CC
. If V
through an NMOS power
BATT
BATT
is internally connected to
is lower than V
pin should be bypassed
OUT
, C3 is shut down and
, is delivered to V
OUT
CC
and V
falls below V
. BATT ON goes
BATT
BATT
BATT
.
OUT
are not
, V
when
BATT
OUT
OUT
CC
CC
,
every preset time-out period (see Figure 11). The reset
active time is adjustable on the LTC695-3.3. An external
push-button reset can be used in connection with the
RESET output. See Push-Button Reset in Applications
Information section.
RESET: Active High Logic Ouput. It is the inverse of
RESET.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the V
falls below the reset voltage threshold (2.90V typically),
LOW LINE goes low. As soon as V
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V
Table 1).
WDI: Watchdog Input. WDI is a three-level input. Driving
WDI either high or low for longer than the watchdog time-
out period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-out period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).
CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT: Logic Output on the Chip Enable Gating Circuit.
When V
a buffered replica of CE IN. When V
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog time-out period. Forcing OSC SEL low,
allows OSC IN to be driven from an external clock signal or
an external capacitor can be connected between OSC IN
and GND.
CC
is above the reset voltage threshold, CE OUT is
CC
drops below V
CC
CC
rises above the reset
CC
is below the reset
input. When V
BATT
(see
CC