S29PL-J SPANSION [SPANSION], S29PL-J Datasheet - Page 23

• Manufacturer Part Number: S29PL-J
• Description: CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

10.2
September 22, 2006 S29PL-J_00_A9
10.1.1
10.1.2
Simultaneous Read/Write Operation
Random Read (Non-Page Read)
Page Mode Read
Address access time (t
access time (t
output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs
(assuming the addresses have been stable for at least t
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. Address bits
Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an
asynchronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t
locations specified by the microprocessor falls within that page) is equivalent to t
CE#2 in PL129J) is deasserted (=V
access has access time of t
is the output control and should be used to gate data to the output inputs if the device is selected. Fast page
mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word
within that page.
In addition to the conventional features (read, program, erase-suspend read, erase-suspend program, and
program-suspend read), the device is capable of reading data from one bank of memory while a program or
erase operation is in progress in another bank of memory (simultaneous operation). The bank can be
selected by bank addresses (PL127J: A22–A20, PL129J and PL064J: A21–A19, PL032J: A20–A18) with
zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
D a t a
Bank 1A
Bank 1B
Bank 2A
Bank 2B
Bank
S h e e t
CE
Bank C
Bank D
Bank A
Bank B
Bank
) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
Word
ACC
( A d v a n c e
) is equal to the delay from stable addresses to valid output data. The chip enable
ACC
CE1#
0
0
1
1
or t
CE
IH
), the reassertion of CE# (CE1# or CE#2 in PL129J) for subsequent
ACC
. Here again, CE# (CE1# /CE#2 in PL129J)selects the device and OE#
S29PL-J
or t
Table 10.3 Page Select
Table 10.4 Bank Select
I n f o r m a t i o n )
CE
CE2#
and subsequent page read accesses (as long as the
1
1
0
0
PL127J: A22–A20, PL064J: A21–A19, PL032J: A20–A18
A2
0
0
0
0
1
1
1
1
ACC
–t
OE
time).
001, 010, 011
100, 101, 110
000
111
A1
0
0
1
1
0
0
1
1
PL129J: A21–A20
01, 10, 11
00, 01, 10
PACC
00
11
. When CE# (CE1# and
A0
0
1
0
1
0
1
0
1
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