S29PL-J SPANSION [SPANSION], S29PL-J Datasheet - Page 61

• Manufacturer Part Number: S29PL-J
• Description: CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

15.7
September 22, 2006 S29PL-J_00_A9
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command.
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and
command following the exceeded time-out may or may not be accepted. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is
input during the time-out period, the normal operation will not be guaranteed. The system must rewrite
the command sequence and any additional addresses and commands. Note that Secured Silicon Sector,
autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data
from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7,
DQ6, DQ2, or RY/BY# in the erasing bank. Refer to
these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
Figure 7.2 on page 15
Operations on page 76
Notes
1. See
2. See the section on DQ3 for information on the sector erase timer.
D a t a
Table 15.1 on page 62
S h e e t
illustrates the algorithm for the erase operation. Refer to the tables in
for parameters, and
for erase command sequence.
( A d v a n c e
No
Figure 15.2 Erase Operation
S29PL-J
Command Sequence
Data Poll to Erasing
Erasure Completed
Bank from System
I n f o r m a t i o n )
Figure 20.8 on page 78
Write Erase
(Notes 1, 2)
Data = FFh?
START
Yes
Write Operation Status on page 64
Embedded
Erase
algorithm
in progress
for timing diagrams.
Table 15.1 on page 62
for information on
Erase/Program
shows the
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