S29PL-J SPANSION [SPANSION], S29PL-J Datasheet - Page 25

• Manufacturer Part Number: S29PL-J
• Description: CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

10.5
10.6
10.7
September 22, 2006 S29PL-J_00_A9
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Note that during
automatic sleep mode, OE# must be at V
specification. ICC5 in
specification.
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (ICC4). If RESET# is held at V
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to the tables in
for the timing diagram.
When the OE# input is at V
placed in the highest Impedance state
Bank
D a t a
Sector
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
S h e e t
AC Characteristic on page 72
DC Characteristics on page 71
Sector Address (A22-A12)
IH
( A d v a n c e
.
READY
IH
Table 10.5 PL127J Sector Architecture (Sheet 1 of 7)
, output from the device is disabled. The output pins (except for RY/BY#) are
00000001XXX
00000010XXX
00000011XXX
00000100XXX
00000101XXX
00000110XXX
00000111XXX
00001000XXX
00001001XXX
00000000000
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
(not during Embedded Algorithms). The system can read data t
S29PL-J
IH
before the device reduces current to the stated sleep mode
I n f o r m a t i o n )
ACC
RP
+ 30 ns. The automatic sleep mode is independent of the
, the device immediately terminates any operation in
for RESET# parameters and to
represents the automatic sleep mode current
Sector Size (Kwords)
IL
READY
but not within V
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
(during Embedded Algorithms). The
SS
±0.3 V, the standby current
Figure 20.5 on page 75
SS
Address Range (x16)
±0.3 V, the device
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
RH
after the
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