S29PL032J SPANSION [SPANSION], S29PL032J Datasheet - Page 24

• Manufacturer Part Number: S29PL032J
• Description: CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

22
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins (For PL129J - CE1#/CE2# pins) to V
CE2# are the power control and select the lower (CE1#) or upper (CE2#) halves
of the device. CE# is the power control. OE# is the output control and gates array
data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to
I
reading array data.
Random Read (Non-Page Read)
Address access time (t
output data. The chip enable access time (t
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least t
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t
(=V
has access time of t
the device and OE# is the output control and should be used to gate data to the
output inputs if the device is selected. Fast page mode accesses are obtained by
keeping Amax–A3 constant and changing A2–A0 to select the specific word within
that page.
CC1
IH
in the DC Characteristics table represents the active current specification for
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
), the reassertion of CE# (CE1# or CE#2 in PL129J) for subsequent access
Word
Table 33
for timing specifications and to
ACC
S29PL127J/S29PL129J/S29PL064J/S29PL032J
PACC
ACC
or t
) is equal to the delay from stable addresses to valid
. When CE# (CE1# and CE#2 in PL129J) is deasserted
CE
Table 3. Page Select
. Here again, CE# (CE1# /CE#2 in PL129J)selects
P R E L I M I N A R Y
ACC
A2
0
0
0
0
1
1
or t
CE
) is the delay from the stable ad-
CE
Figure 11
IH
and subsequent page read ac-
.
IL
. In PL129J, CE1# and
for the timing diagram.
A1
0
0
1
1
0
0
ACC
–t
OE
time).
31107A62 April 7, 2005
A0
0
1
0
1
0
1