CY7C1081DV33-12BAXI CYPRESS [Cypress Semiconductor], CY7C1081DV33-12BAXI Datasheet - Page 5

• Manufacturer Part Number: CY7C1081DV33-12BAXI
• Description: 64-Mbit (4 M x 16) Static RAM 2.0-V data retention
• Manufacturer: CYPRESS [Cypress Semiconductor]

Data Retention Characteristics
Over the Operating Range
Notes
Document #: 001-53992 Rev. *C
V
I
t
t
2. Valid SRAM operation does not occur until the power supplies reach the minimum operating V
3. Tested initially and after any design or process changes that may affect these parameters.
4. Full device operation requires linear V
CCDR
CDR
R
DR
[4]
normal SRAM operation begins to include reduction in V
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
[3]
OUTPUT
Parameter
CE
CE
V
CC
1
2
Z
0
(a)
= 50 
V
Data retention current
Chip deselect to data
retention time
Operation recovery time
CC
for data retention
Description
CC
ramp from V
30 pF*
50 
RISE TIME:
GND
3.0 V
t
CDR
3.0 V
> 1 V/ns
Figure 2. AC Test Loads and Waveforms
DR
V
Figure 3. Data Retention Waveform
DD
to V
TH
10%
to the data retention (V
= 1.5 V
90%
CC
V
V
(min) > 50 s or stable at V
CC
IN
> V
= 2 V, CE
DATA RETENTION MODE
ALL INPUT PULSES
CC
– 0.2 V or V
1
V
(c)
> V
DR
Conditions
CCDR
> 2 V
CC
, 2.0 V) voltage.
– 0.2 V, CE
CC
IN
(min) > 50 s.
DD
< 0.2 V
(3.0 V). 100 s (t
90%
HIGH-Z CHARACTERISTICS:
2
10%
< 0.2 V,
FALL TIME:
> 1 V/ns
[2]
OUTPUT
power
3.0 V
INCLUDING
JIG AND
SCOPE
t
) after reaching the minimum operating V
3.3 V
Min
R
12
2
–
0
5 pF*
CY7C1081DV33
Typ
–
–
–
–
(b)
R1 317 
Max
100
–
–
–
Page 5 of 13
351
R2
Unit
mA
ns
ns
V
DD
,
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