CY7C1081DV33-12BAXI CYPRESS [Cypress Semiconductor], CY7C1081DV33-12BAXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1081DV33-12BAXI
• Description: 64-Mbit (4 M x 16) Static RAM 2.0-V data retention
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Truth Table
Document #: 001-53992 Rev. *C
Note
CE
18. CE refers to the internal logical combination of CE
ADDRESS
BHE, BLE
H
X
L
L
L
L
L
L
L
DATA I/O
1
CE
WE
CE
H
H
H
H
H
H
H
X
L
2
OE
X
X
X
X
X
H
L
L
L
WE
X
X
H
H
H
H
L
L
L
BLE BHE
X
X
H
H
X
L
L
L
L
(continued)
t
SA
X
X
H
H
X
L
L
L
L
Figure 8. Write Cycle 3 (BLE or BHE Controlled)
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
High-Z
High-Z
I/O
1
and CE
0
– I/O
t
AW
2
such that when CE
7
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
I/O
8
– I/O
t
WC
15
1
is LOW and CE
Read all bits
Write all bits
Power down
Power down
Read lower bits only
Read upper bits only
Write lower bits only
Write upper bits only
Selected, Outputs disabled
t
t
BW
t
PWE
SCE
DATA
IN
2
t
SD
VALID
is HIGH, CE is LOW. For all other combinations, CE is HIGH.
Mode
[18]
t
HD
t
HA
Standby (I
Standby (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
CY7C1081DV33
CC
CC
CC
CC
CC
CC
CC
SB
SB
)
)
)
)
)
)
)
Power
)
)
Page 9 of 13
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