CY7C1081DV33-12BAXI CYPRESS [Cypress Semiconductor], CY7C1081DV33-12BAXI Datasheet - Page 7

• Manufacturer Part Number: CY7C1081DV33-12BAXI
• Description: 64-Mbit (4 M x 16) Static RAM 2.0-V data retention
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes
Document #: 001-53992 Rev. *C
11. Device is continuously selected. OE, CE
12. WE is HIGH for read cycle.
13. Address valid before or similar to CE
14. CE refers to the internal logical combination of CE
DATA OUT
ADDRESS
DATA OUT
CURRENT
ADDRESS
BHE, BLE
SUPPLY
V
OE
CE
CC
PREVIOUS DATA VALID
HIGH IMPEDANCE
1
Figure 4. Read Cycle 1 (Address Transition Controlled)
transition LOW and CE
t
t
LZCE
PU
1
= V
IL
Figure 5. Read Cycle 2 (OE Controlled)
, BHE or BHE or both = V
t
t
ACE
OHA
t
1
t
LZBE
t
DBE
LZOE
and CE
t
DOE
50%
2
2
transition HIGH.
such that when CE
t
AA
IL
, and CE
t
RC
1
t
is LOW and CE
RC
2
= V
IH
.
2
DATA VALID
is HIGH, CE is LOW. For all other combinations, CE is HIGH.
[12, 13, 14]
[11, 12]
t
DATA VALID
HZOE
t
t
HZCE
HZBE
CY7C1081DV33
t
PD
50%
IMPEDANCE
HIGH
Page 7 of 13
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