CY7C1081DV33-12BAXI CYPRESS [Cypress Semiconductor], CY7C1081DV33-12BAXI Datasheet - Page 6

• Manufacturer Part Number: CY7C1081DV33-12BAXI
• Description: 64-Mbit (4 M x 16) Static RAM 2.0-V data retention
• Manufacturer: CYPRESS [Cypress Semiconductor]

AC Switching Characteristics
Over the Operating Range
Notes
Document #: 001-53992 Rev. *C
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
5. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read
6. t
7. t
8. These parameters are guaranteed by design and are not tested.
9. The internal memory write time is defined by the overlap of WE, CE
10. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
cycle use output loading shown in part a) of
initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the
signal that terminates the write.
power
HZOE
, t
is the minimum amount of time that the power supply must be at typical V
Parameter
HZCE
, t
[9, 10]
HZWE
, t
HZBE
and t
[5]
LZOE
V
Read cycle time
Address to data valid
Data hold from address change
CE
OE LOW to data valid
OE LOW to low-Z
OE HIGH to high-Z
CE
CE
CE
CE
Byte enable to data valid
Byte enable to low-Z
Byte disable to high-Z
Write cycle time
CE
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low-Z
WE LOW to high-Z
Byte enable to end of write
CC
, t
1
1
1
1
1
1
(typ) to the first access
LZCE
LOW and CE
LOW and CE
HIGH and CE
LOW and CE
HIGH and CE
LOW and CE
, t
AC Test Loads and Waveforms
\LZWE
, t
LZBE
2
2
2
2
2
2
[7]
are specified with a load capacitance of 5 pF as in (b) of
HIGH to Data Valid
HIGH to low-Z
HIGH to power-up
HIGH to write end
[7]
[7]
LOW to high-Z
LOW to power-down
Description
1
[6]
= V
IL
, and CE
[2]
, unless specified otherwise.
[7]
[7]
CC
[8]
2
values until the first memory access can be performed.
= V
[8]
IH
HZWE
. Chip enables must be active and WE and byte enables must be LOW to
and t
SD
.
AC Test Loads and Waveforms
Min
100
12
12
–
3
–
–
1
–
3
–
0
–
–
1
–
9
9
0
0
9
7
0
3
–
9
–12
CY7C1081DV33
Max
12
12
12
–
–
–
7
–
7
–
7
–
7
–
7
–
–
–
–
–
–
–
–
–
7
–
[2]
.
Page 6 of 13
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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