PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 11

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

Name
P_TRDY#
P_DEVSEL#
P_STOP#
P_LOCK#
P_IDSEL
P_PERR#
P_SERR#
P_REQ#
P_GNT#
P_RST#
Pin #
B15
D21
C4
C14
B19
C8
B4
B21
C20
E22
Page 11 of 77
Type
STS
STS
STS
STS
OD
TS
I
I
I
I
Description
Primary TRDY (Active LOW). Driven by the target of
a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven HIGH for one cycle.
Primary Device Select (Active LOW). Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C21P100 waits for the
assertion of this signal within 5 cycles of P_FRAME#
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven HIGH for one cycle.
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to stop
the current transaction. Before tri-stated, it is driven
HIGH for one cycle.
Primary LOCK (Active LOW). Asserted by an
initiator, one clock cycle after the first address phase of a
transaction, attempting to perform an operation that may
take more than one PCI transaction to complete.
Primary ID Select. Used as a chip select line for Type
0 configuration access to PI721P100 configuration
space.
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven
HIGH for one cycle.
Primary System Error (Active LOW). Can be driven
LOW by any device to indicate a system error condition.
PI7C21P100 drives this pin on:
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW): This is asserted by
PI7C21P100 to indicate that it wants to start a
transaction on the primary bus. PI7C21P100 de-asserts
this pin for at least 2 PCI clock cycles before asserting it
again.
Primary Grant (Active LOW): When asserted,
PI7C21P100 can access the primary bus. During idle
and P_GNT# asserted, PI7C21P100 will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW): When P_RESET# is
active, all PCI signals should be asynchronously tri-
stated.
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100