PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 53

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.38
8.1.39
EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h
ARBITER MODE REGISTER – OFFSET 50h
BIT
2
1:0
BIT
11:10
9:8
BIT
15:8
7
6
5:2
1
FUNCTION
Downstream Memory
Read Prefetching
Dynamic Control
RESERVED
FUNCTION
Minimum Free Space in
Memory Data FIFO
Control (Secondary)
Minimum Free Space in
Memory Data FIFO
Control (Primary)
FUNCTION
Arbiter Fairness
Counter
GNT# Output Toggling
Enable
Broken Master Refresh
RESERVED
Broken Master Timeout
Enable
TYPE
TYPE
TYPE
RW
RO
RW
RW
RW
RW
RW
RO
RW
Page 53 of 77
DESCRIPTION
Downstream Memory Read Prefetching Dynamic Control
0: Enable downstream memory read prefetching dynamic control
1: Disable downstream memory read prefetching dynamic control
Reset to 0
(Described in section 4.3.6)
Reserved. Returns 00 when read.
DESCRIPTION
Minimum Free Space in Memory Data FIFO Control
(Secondary)
Selects the minimum free space in the memory data FIFO to accept
memory writes on the secondary bus in PCI-X mode
00: 128 bytes of free space to accept memory writes
01: 256 bytes of free space to accept memory writes
10: 512 bytes of free space to accept memory writes
11: 128 bytes of free space to accept memory writes
Reset to 00
Minimum Free Space in Memory Data FIFO Control (Primary)
Selects the minimum free space in the memory data FIFO to accept
memory writes on the primary bus in PCI-X mode
00: 128 bytes of free space to accept memory writes
01: 256 bytes of free space to accept memory writes
10: 512 bytes of free space to accept memory writes
11: 128 bytes of free space to accept memory writes
Reset to 00
DESCRIPTION
Arbiter Fairness Counter
These bits are the initialization value of a counter used by the internal
arbiter. It controls the number of PCI bus cycles that the arbiter holds
a device’s PCI bus grant active after detecting a PCI bus request from
another device. The counter is reloaded whenever a new PCI bus
grant is asserted. For every new PCI bus grant, the counter is armed
to decrement when it detects the de-assertion of FRAME#. If the
arbiter fairness counter is set to 00h, the arbiter will not remove a
device’s PCI bus grant until the device has de-asserted its PCI bus
request.
Reset to 08h
GNT# Output Toggling Enable
0: GNT# not de-asserted after granted master asserts FRAME#
1: GNT# de-asserts for 1 clock after 2 clocks from the granted master
asserting FRAME#.
Reset to 0
Broken Master Refresh
0: A broken master will be ignored forever except when it de-asserts
its REQ# for at least 1 clock
1: Refresh broken master state after all other masters have been
served once.
Reset to 0
Reserved. Returns 0000 when read.
Broken Master Timeout Enable
0: Broken master timeout disabled
1: Broken master timeout enabled. This enables the internal arbiter to
count 16 PCI bus cycles while waiting for FRAME# to become
active when a device’s PCI bus GNT# is active and the PCI bus is
idle. If the broken master timeout expires, the PCI bus GNT# for the
device is de-asserted.
Reset to 0
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100