PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 14

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

3.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION
Name
S_SERR#
S_REQ[6:2]#
S_REQ[1]#
S_GNT[6:2]#
S_GNT[1]#
S_RST#
Name
S_AD[63:32]
S_CBE[7:4]#
Pin #
AB19
AC3, AB5, AB3,
W2, AA2
AA23
AC4, AB4, AC5, Y2,
AB1
AA19
U23
Pin #
AB8, AB7, AA7,
AB6, AA6, AA5, Y6,
Y3, V2, V4, U2, U3,
T2, T3, R2, R3, P2,
Y1, P3, W1, P4, U1,
N2, N3, M2, M3, R1,
L2, L3, K2, K3, K4
Y10, AB10, AA11,
AC8
Page 14 of 77
Type
Type
TS
TS
TS
TS
O
I
I
I
Description
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system error
condition.
Secondary Request (Active LOW): This is asserted by
an external device to indicate that it wants to start a
transaction on the secondary bus. The input is externally
pulled up through a resistor to VDD.
Secondary Request (Active LOW):
When the internal arbiter is enabled, this is asserted by
an external device to indicate that it wants to start a
transaction on the secondary bus. The input is externally
pulled up through a resistor to VDD.
When the internal arbiter is disabled, this is used by
PI7C21P100 as its GNT input.
Secondary Grant (Active LOW): PI7C21P100 asserts
these pins to allow external masters to access the
secondary bus. PI7C21P100 de-asserts these pins for at
least 2 PCI clock cycles before asserting it again.
During idle and S_GNT# deasserted, PI7C21P100 will
drive S_AD, S_CBE, and S_PAR.
Secondary Grant (Active LOW):
When the internal arbiter is enabled, PI7C21P100 asserts
this pin to allow external masters to access the
secondary bus. PI7C21P100 de-asserts this pin for at
least 2 PCI clock cycles before asserting it again.
During idle and S_GNT# deasserted, PI7C21P100 will
drive S_AD, S_CBE, and S_PAR.
When the internal arbiter is disabled, this is used by
PI7C21P100 as its REQ output.
Secondary RESET (Active LOW): Asserted when any
of the following conditions are met:
1.
2.
3.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, S_PAR, and
S_PAR64.
Description
Secondary Upper 32-bit Address/Data: Multiplexed
address and data bus. Address is indicated by
S_FRAME# assertion. Write data is stable and valid
when S_IRDY# is asserted and read data is stable and
valid when S_IRDY# is asserted. Data is transferred on
rising clock edges when both S_IRDY# and S_TRDY#
are asserted. During bus idle, PI7C21P100 drives S_AD
to a valid logic level when the bridge is granted the bus.
Secondary Upper 32-bit Command/Byte Enables:
Multiplexed command field and byte enable field.
During address phase, the initiator drives the transaction
type on these pins. The initiator then drives the byte
enables during data phases. During bus idle,
PI7C21P100 drives S_CBE[7:0] to a valid logic level
when the bridge is granted the bus.
Signal P_RESET# is asserted.
Secondary reset bit in bridge control register in
configuration space is set.
The chip reset bit in the chip control register in
configuration space is set.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100