PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 39

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

7.5
7.6
7.7
devices should not implement a device number 15 (i.e., S_AD(31)). The device mask bit
options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by PI7C21P100 allow architectures
to support private device groupings that use a single or multiple interrupt binding.
ADDRESS PARITY ERRORS
PI7C21P100 checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C21P100 detects an address parity error, the transaction will not be
claimed and will be allowed to terminate with a master abort. The result of an address parity
error will be controlled by the parity error response bits in both the command and bridge
control registers.
OPTIONAL BASE ADDRESS REGISTER
The 64 bit Base Address register located in the configuration register at offsets 10h and 14h
can optionally be used to acquire a 1 MB memory region at system initialization. PI7C21P100
uses this register to claim an additional prefetchable memory region for the secondary bus.
When used with the secondary device masking, this allows for the acquisition of memory
space for private devices that are not otherwise viewable by the system software.
This 64 bit base address register and the memory space defined by it are enabled by the
BAR_EN. When BAR_EN is pulled LOW, this register location returns zeros for reads and
cannot be written. When BAR_EN is pulled HIGH, the upper memory base address register
and lower memory base address registers combined specify address bits 63:20 of a memory
region. Memory accesses on the primary bus are compared against this register, if address bits
63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory
base address register and the upper memory base address register, the access is claimed by
PI7C21P100 and passed through to the secondary bus. Memory accesses on the secondary bus
are also compared against this register, if address bits 63:20 are equal to bits 63:20 of the
address defined by the combination of the lower memory base address register and the upper
memory base address register, the access is ignored by the bridge.
OPTIONAL CONFIGURATION ACCESS FROM THE
SECONDARY BUS
PI7C21P100 accepts Type 0 configuration transactions when the following conditions are met
during the address phase:
Applications that require access to the bridge configuration registers via the secondary bus
may control the initialization sequence through the P_CFG_BUSY pin and bit[2] offset 44h of
the miscellaneous control register. When P_CFG_BUSY is pulled HIGH, bit[2] offset 44h is
set to 1b at power up and reset. This causes PI7C21P100 to retry Type 0 configuration
transactions on the primary bus that would otherwise be accepted. PI7C21P100 continues to
retry these transactions until bit[2] offset 44h is set to 0b by a configuration write initiated on
the secondary bus. This allows a device on the secondary bus to initialize the bridge and any
private devices on the secondary bus without contention from devices accessing the bridge
S_CBE[3:0]# indicates a configuration read or configuration write transaction
S_AD[1:0] are 00
S_IDSEL is asserted
Page 39 of 77
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100