PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 22

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

4
4.1
Table 4-1 PCI AND PCI-X TRANSACTIONS
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C21P100, and transaction termination. The PI7C21P100 has two 2KB buffers for read
data buffering of upstream and downstream transactions. Also, PI7C21P100 has two 1KB
buffers for write data buffering of upstream and downstream transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI and PCI-X transactions performed by PI7C21P100.
Table 4-1 lists the command code and name of each PCI and PCI-X transaction. The Master
and Target columns indicate support for each transaction when PI7C21P100 initiates
transactions as a master, on the primary and secondary buses, and when PI7C21P100
responds to transactions as a target, on the primary and secondary buses.
As indicated in Table 4-1, the following commands are not supported by PI7C21P100:
PI7C21P100 ignores reserved command codes.
interrupt acknowledge transactions as a target.
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the transaction as a
target. To generate special cycle transactions on other buses, either upstream or downstream,
Type 1 configuration write must be used.
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PI7C21P100 never initiates a transaction with a reserved command code and, as a target,
PI7C21P100 does not generate interrupt acknowledge transactions. PI7C21P100 ignores
PI7C21P100 does not respond to special cycle transactions. PI7C21P100 cannot
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Page 22 of 77
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
PI7C21P100
N
N
Y
Y
N
N
Y
N
N
Y (Type 0 only)
Y
Y
Y
Y
Secondary
Y
Y