CY7C1380D CYPRESS [Cypress Semiconductor], CY7C1380D Datasheet

CY7C1380D

Manufacturer Part Number

CY7C1380D

Description

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1380D.pdf (29 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1380D-167AC

Manufacturer:

CYPRESS

Quantity:

748

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1380D-167AXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

CY7C1380D-167AXC

Manufacturer:

CYPRESS/赛普拉斯

Quantity:

20 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1380D-167AXCT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1380D-167AXI

Manufacturer:

CYPRESS

Quantity:

1 100

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1380D-167AXI

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1380D-167AXIT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1380D-167BZC

Manufacturer:

CYPRESS

Quantity:

364

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1380D-167BZC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Amily Shenzhen XNWY Technology Co., Ltd

Part Number:

CY7C1380D-200AXC

Current page: 1 of 29
Download datasheet (469Kb)

Cypress Semiconductor Corporation

Document #: 38-05543 Rev. *A

Features

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in JEDEC-standard lead-free 100-pin TQFP,

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE

— 2.6 ns (for 250-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

Pentium interleaved or linear burst sequences

119-ball BGA and 165-Ball fBGA packages

, CE

are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

•

3901 North First Street



PRELIMINARY

Functional Description

The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36

and 1,048,576 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable ( CE

Enables (CE

and ADV ), Write Enables ( BW

( GW ). Asynchronous inputs include the Output Enable ( OE )

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor ( ADSP ) or

Address Strobe Controller ( ADSC ) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin ( ADV ).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1380D/CY7C1382D operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

250 MHz

350

2.6

•

San Jose

and CE

200 MHz

[2]

300

3.0

), Burst Control inputs ( ADSC , ADSP ,

CA 95134

[1]

, and BWE ), and Global Write

167 MHz

Revised October 28, 2004

), depth-expansion Chip

275

3.4

•

CY7C1380D

CY7C1382D

408-943-2600

Unit

Related parts for CY7C1380D

Related keywords

CY7C1380D datasheet
CY7C1380D data sheet
CY7C1380D pdf datasheet
CY7C1380D component
CY7C1380D part
CY7C1380D distributor
CY7C1380D RoHS
CY7C1380D datasheet download