CY7C1380D CYPRESS [Cypress Semiconductor], CY7C1380D Datasheet - Page 21

• Manufacturer Part Number: CY7C1380D
• Description: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05543 Rev. *A
Switching Waveforms
Read Cycle Timing
Notes:
26. On this diagram, when CE is LOW: CE
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
GW, BWE,
ADDRESS
ADSC
ADSP
BWx
ADV
CLK
OE
CE
t
ADS
t AS
t CES
[26]
A1
t
ADH
t AH
t CEH
t
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
t CO
1
is LOW, CE
t ADS
A2
Q(A1)
t ADH
t OEHZ
2
t ADVS
is HIGH and CE
t ADVH
t OELZ
t OEV
PRELIMINARY
DON’T CARE
Q(A2)
t DOH
3
t CO
is LOW. When CE is HIGH: CE
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
X
LOW .
Q(A2 + 2)
BURST READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
CY7C1380D
CY7C1382D
3
Q(A2 + 1)
is HIGH.
t CHZ
Deselect
cycle
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