CY7C1380D CYPRESS [Cypress Semiconductor], CY7C1380D Datasheet - Page 14

• Manufacturer Part Number: CY7C1380D
• Description: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05543 Rev. *A
Scan Register Sizes
Identification Codes
Instruction
Bypass
ID
Boundary Scan Order
(119-ball BGA package)
Boundary Scan Order
(165-ball fBGA package)
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Register Name
Code
000
001
010
100
101
011
110
111
Bit Size (x36)
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
32
85
89
3
1
Bit Size (x18)
PRELIMINARY
32
85
89
3
1
Description
CY7C1380D
CY7C1382D
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