CY7C1380D CYPRESS [Cypress Semiconductor], CY7C1380D Datasheet - Page 8

• Manufacturer Part Number: CY7C1380D
• Description: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05543 Rev. *A
Burst Sequences
The CY7C1380D/CY7C1382D provides a two-bit wraparound
counter, fed by A1: A0, that implements either an interleaved
or linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
Address
Parameter
after the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) .
A1: A0
First
1
00
01
10
11
, CE
2
Operation
, and CE
[ 3, 4, 5, 6, 7, 8]
3
Address
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Second
are available only in the TQFP package. BGA package has only two chip selects CE
A1: A0
01
00
10
11
Add. Used
Address
Description
External
External
External
External
External
A1: A0
Third
None
None
None
None
None
None
Next
Next
10
11
00
01
CE
H
X
X
X
L
L
L
L
L
L
L
L
L
Address
Fourth
A1: A0
1
PRELIMINARY
10
01
00
11
CE
X
X
X
X
H
H
H
H
H
X
X
L
L
2
CE
H
H
X
X
X
X
X
X
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
3
Linear Burst Address Table (MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
ZZ ADSP
H
L
L
L
L
L
L
L
L
L
L
L
L
X
Address
Test Conditions
A1: A0
DD
DD
is valid. Appropriate write will be done based on which byte write is active.
First
00
01
10
11
– 0.2V
– 0.2V
H
H
H
H
H
X
X
H
H
L
L
L
L
ADSC
X
X
X
X
X
H
H
L
L
L
L
L
L
Address
Second
1
A1: A0
and CE
01
10
00
11
X
1
. Writes may occur only on subsequent clocks
, CE
ADV WRITE OE CLK
X
X
X
X
X
X
X
X
X
X
X
L
L
2
.
2
, CE
2t
Min.
CYC
0
Address
H
H
H
X
X
X
X
X
X
X
X
H
3
L
A1: A0
, ADSP, and ADSC must
Third
ZZREC
10
11
00
01
CY7C1380D
CY7C1382D
2t
2t
H
X
X
X
X
X
X
H
X
H
L
L
L
Max.
80
CYC
CYC
after the ZZ input
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
X
Page 8 of 29
Address
Fourth
A1: A0
Tri-State
11
00
01
10
Unit
mA
ns
ns
ns
ns
DQ
Q
D
Q
Q