APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 57

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Module Delays
Figure 1-29 • Module Delays
Sample Macrocell Library Listing
Table 1-45 • Worst-Case Military Conditions
Cell Name
NAND2
AND2
NOR3
MUX2L
OA21
XOR2
LDL
DFFL
Notes:
1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of
2. All –F parts are only available as commercial.
3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.
local interconnect.
V
DD
2-Input NAND
2-Input AND
3-Input NOR
2-1 MUX with Active Low Select
2-Input OR into a 2-Input AND
2-Input Exclusive OR
Active Low Latch (LH/HL)
CLK-Q
t
t
Negative Edge-Triggered D-type Flip-Flop (LH/HL)
CLK-Q
t
t
setup
hold
setup
hold
= 2.3 V, T
J
= 70º C, T
C
A
B
Y
J
= 70°C, T
Description
t
50%
DALH
1
50%
50%
J
= 125°C for Military/MIL-STD-883
t
DAHL
50% 50%
A
B
C
t
50%
DBLH
v5.7
50%
t
Y
DBHL
50%50%
t
DCLH
50%
LH
HL
LH
HL
3
3
3
3
50%
t
DCHL
Max
0.5
0.5
0.7
0.8
0.8
0.6
0.9
0.8
0.9
0.8
Std.
50%
Min
0.7
0.1
0.6
0.0
ProASIC
Max
0.6
0.8
1.0
0.6
1.0
0.8
1.1
0.9
1.1
1.0
PLUS
–F
Flash Family FPGAs
2
Min
0.8
0.2
0.7
0.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-51