APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 67

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APA075-BGB

Manufacturer Part Number
APA075-BGB
Description
ProASIC Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Synchronous Write and Read to the Same Location
Note: The plot shows the normal operation status.
Figure 1-37 • Synchronous Write and Read to the Same Location
Table 1-56 • T
Symbol t
CCYC
CMH
CML
WCLKRCLKS
WCLKRCLKH
OCH
OCA
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write
3. If WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
5. All –F speed grade devices are 20% slower than the standard numbers.
clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS
and RCLKS driven by the same design signal.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Cycle time
Clock high phase
Clock low phase
WCLKS ↑ to RCLKS ↑ setup time
WCLKS ↑ to RCLKS ↑ hold time
Old DO valid from RCLKS ↑
New DO valid from RCLKS ↑
WCLKS
RCLKS
t WCLKRCLKH
t WCLKRCLKS
* New data is read if WCLKS ↑ occurs before setup time.
DO
The data stored is read if WCLKS ↑ occurs after hold time.
Last Cycle Data
t OCH
t OCA
DD
Description
DD
= 2.3 V to 2.7 V for Commercial/industrial
= 2.3 V to 2.7 V for Military/MIL-STD-883
t CMH
t CCYC
v5.7
Min.
– 0.1
7.5
3.0
3.0
7.5
t CML
Max.
7.0
3.0
New Data*
Units
ns
ns
ns
ns
ns
ns
ns
ProASIC
OCA/OCH displayed for
Access Timed Output
PLUS
Flash Family FPGAs
Notes
1-61

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