APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 66

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Synchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 1-36 • Synchronous SRAM Write
Table 1-55 • T
1 -6 0
Symbol t
CCYC
CMH
CML
DCH
DCS
WACH
WDCS
WPCA
WPCH
WRCH, WBCH WRB & WBLKB hold from WCLKS ↑
WRCS, WBCS
Notes:
1. On simultaneous read and write accesses to the same location, DI is output to DO.
2. All –F speed grade devices are 20% slower than the standard numbers.
ProASIC
PLUS
xxx
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
Cycle time
Clock high phase
Clock low phase
DI hold from WCLKS ↑
DI setup to WCLKS ↑
WADDR hold from WCLKS ↑
WADDR setup to WCLKS ↑
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
WRB & WBLKB setup to WCLKS ↑
WRB, WBLKB
t WRCH , t WBCH
t WRCS , t WBCS
WADDR, DI
t DCS , t WDCS
WCLKS
WPE
t DCH , t WACH
Description
t WPCH
DD
DD
= 2.3 V to 2.7 V for Commercial/industrial
= 2.3 V to 2.7 V for Military/MIL-STD-883
Cycle Start
t WPCA
t CMH
v5.7
Min.
7.5
3.0
3.0
0.5
1.0
0.5
1.0
3.0
0.5
1.0
t CCYC
Max.
0.5
t CML
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WPE is invalid while
PARGEN is active
Notes