CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet - Page 10

• Manufacturer Part Number: CY7C68000A
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08052 Rev. *F
HS/FS Interface Timing–30 MHz
Table 4. 30 MHz Timing Interface Timing Constraints Parameters
Table 5. Tri-state Mode Timing Constraints Parameters
T
T
T
T
T
T
T
T
T
T
T
CSU_MIN
CH_MIN
DSU_MIN
DH_MIN
CCO
CDO
VSU_MIN
VH_MIN
CVO
tssu
tspd
Parameter
Parameter
Minimum set-up time for TXValid
Minimum hold time for TXValid
Minimum set-up time for Data (Transmit direction)
Minimum hold time for Data (Transmit direction)
Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
Clock to Data out time (Receive direction)
Minimum set-up time for ValidH (transmit Direction)
Minimum hold time for ValidH (Transmit direction)
Clock to ValidH out time (Receive direction)
Minimum set-up time for Tri-state
Propagation Delay for Tri-State mode
Control_Out
Control_In
DataOut
Output / IO
DataIn
Suspend
Tri-state
CLK
Figure 4. 30-MHz Timing Interface Timing Constraints
TDSU_MIN
TCSU_MIN
TVSU_MIN
Description
Description
Figure 5. Tri-state Mode Timing Constraints
XXXX
Ttssu Ttspd
TCH_MIN
TDH_MIN
TVH_MIN
Hi-Z
TCDO
TCCO
TCVO
Min.
Min.
16
16
16
1
1
1
1
1
1
0
Typ.
Typ.
Ttspd
Max.
Max.
20
20
20
50
CY7C68000A
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Notes
Notes