CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet - Page 6

• Manufacturer Part Number: CY7C68000A
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08052 Rev. *F
Table 1. Pin Descriptions
QFN VFBGA
18
15
14
54
21
22
23
1
C1
B6
B5
A5
A8
A4
B7
A6
LineState0
OpMode1
OpMode0
TXValid
TXReady
RXValid
RXActive
RXError
Name
[1]
(continued)
Output
Output
Output
Output
Output
Type
Input
Input
Input
Default
Line State These signals reflect the current state of the single-ended
receivers. They are combinatorial until a ‘usable’ CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
00–0: SE0
01–1: ‘J’ State
10–2: ‘K’ State
11–3: SE1
Operational Mode These signals select among various operational
modes.
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved
Operational Mode These signals select among various operational
modes.
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved
Transmit Valid This signal indicates that the data bus is valid. The asser-
tion of Transmit Valid initiates SYNC on the USB. The negation of Trans-
mit Valid initiates EOP on the USB. The start of SYNC must be initiated
on the USB no less than one or no more that two CLKs after the assertion
of TXValid.
In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the
USB between 8- and 16-bit times after the assertion of TXValid is detected
by the Transmit State Machine.
In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less
than one or more than two CLKs after the assertion of TXValid is detected
by the Transmit State Machine.
Transmit Data Ready If TXValid is asserted, the SIE must always have
data available for clocking in to the TX Holding Register on the rising edge
of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge
of CLK, the CY7C68000A will load the data on the data bus into the TX
Holding Register on the next rising edge of CLK. At that time, the SIE
should immediately present the data for the next transfer on the data bus
Receive Data Valid This signal indicates that the DataOut bus has valid
data. The Receive Data Holding Register is full and ready to be unloaded.
The SIE is expected to latch the DataOut bus on the clock edge.
Receive Active This signal indicates that the receive state machine has
detected SYNC and is active.
RXActive is negated after a bit stuff error or an EOP is detected.
Receive Error
0 Indicates no error.
1 Indicates that a receive error has been detected.
Description
CY7C68000A
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