CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet - Page 5

• Manufacturer Part Number: CY7C68000A
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08052 Rev. *F
Table 1. Pin Descriptions
QFN VFBGA
49
48
46
44
43
41
39
38
37
36
34
33
31
29
27
26
50
12
13
24
19
3
2
G8
G7
G5
G3
G2
G4
D8
G1
C2
F8
F6
F5
F4
F3
F1
E1
E2
A1
B2
B3
B4
B1
B8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CLK
Reset
XcvrSelect
TermSelect
Suspend
Tri_state
LineState1
Name
[1]
(continued)
Output
Output
Type
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Default
N/A
N/A
N/A
N/A
Bidirectional Data Bus This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the
16-bit mode. Under the 8-bit unidirectional mode, these bits are used as
inputs for data, selected by the RxValid signal.
Bidirectional Data Bus This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the 8-
bit bidirectional mode. Under the 8-bit unidirectional mode these bits are
used as outputs for data, selected by the TxValid signal.
Clock This output is used for clocking the receive and transmit parallel
data on the D[15:0] bus.
Active HIGH Reset Resets the entire chip. This pin can be tied to V
through a 0.1-µF capacitor and to GND through a 100 K resistor for a
10-ms RC time constant.
Transceiver Select This signal selects between the Full-Speed (FS) and
the High-Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
Termination Select This signal selects between the between the Full
Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination
Suspend Places the CY7C68000A in a mode that draws minimal power
from supplies. Shuts down all blocks not necessary for Suspend/Resume
operations. While suspended, TermSelect must always be in FS mode
to ensure that the 1.5 Kohm pull up on DPLUS remains powered.
0: CY7C68000A circuitry drawing suspend current
1: CY7C68000A circuitry drawing normal current
Tri-state Mode Enable Places the CY7C68000A into Tri-state mode
which tri-states all outputs and IO’s. Tri-state Mode can only be enabled
while suspended.
0: Disables Tri-state Mode
1: Enables Tri-state Mode
Line State These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
Description
CY7C68000A
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