CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 10

• Manufacturer Part Number: CY7C68310
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.2.2
The ATA Command Block 2 (ATACB2) functionality provides a
means of passing ATA commands and ATA register accesses
for execution. ATACB2 allows for 48-bit commands. ATACB2
commands are transferred in the CBWCB portion of the CBW.
The ATACB2 is distinguished from other command blocks by
the first two bytes of the command block matching the
Table 5-2. ATACB2 Field Descriptions
Document 38-08030 Rev. *H
Byte
0
1
2
3
ATA Command Block 2 (ATACB2)
bVSCBSignature
bVSCBSubCommand
bmATACB2RegisterSelect
bmATACB2ActionSelect1
Field Name
This field indicates to the CY7C68310 that the ATACB contains a vendor-
This field must be set to 0x025h for ATACB2 commands.
This field controls which of the taskfile register read or write accesses occur.
This field controls the execution of the ATACB2 according to the bitfield values:
specific command block. This value of this filed must match the value in
EEPROM address 0x06h for this vendor-specific command to be recognized.
Taskfile read data will always be 12 bytes in length, and unselected register data
will be returned as 0x00h. Register accesses occur in sequential order as
outlined below (0 to 7):
Bit 0 (3F6h) - Alternate Status (read only, unaffected by write commands)
Bit 1 (1F1h) - Features / Error
Bit 2 (1F2h) - Sector Count
Bit 3 (1F3h) - LBA Low (Sector Number)
Bit 4 (1F4h) - LBA Mid (Cylinder Low)
Bit 5 (1F5h) - LBA High (Cylinder High)
Bit 6 (1F6h) - Device / Head (see bmATACB2ActionSelect1)
Bit 7 (1F7h) - Command / Status
Bit 7 IdentifyDevice - This bit indicates that the data phase of the command will
contain ATAPI (0xA1h) or ATA (0xECh) IDENTIFY device data. Setting Identi-
fyDevice when the data phase does not contain IDENTIFY device data will result
in undetermined device behavior.
0 = Data phase does not contain IDENTIFY device data
1= Data phase contains ATAPI or ATA IDENTIFY device data
Bit 6 UDMACommand - This bit enables supported UDMA device transfers.
Setting this bit when a non-UDMA capable device is attached will result in
undetermined behavior.
0 = Do not use UDMA device transfers (only use PIO mode)
1= Use UDMA device transfers
Bit 5 DEVOverride - This bit determines whether the DEV bit value is taken from
the CY7C68310 configuration data or from the ATACB2.
0 = The DEV bit will be taken from EEPROM address 0x05h, bit 5
1= The DEV bit will be taken from bATACB2DeviceHeadData[5]
Bit 4 DErrorOverride - This bit controls the device error override feature. This
bit should not be set during a bmATACB2ActionSelect TaskFileRead.
0 = Data accesses are halted if a device error is detected
1 = Data accesses are not halted if a device error is detected
Bit 3 PErrorOverride - This bit controls the phase error override feature. This bit
should not be set during a bmATACB2ActionSelect TaskFileRead.
0 = Data accesses are halted if a phase error is detected
1 = Data accesses are not halted if a phase error is detected
Bit 2 PollAltStatOverride - This bit determines whether or not the Alternate Status
register will be polled and its BSY bit will be used to qualify the start of ATACB
operation.
0 = The AltStat register will be polled until BSY=0 before proceeding with the
ATACB operation
1= The ATACB operation will be executed without polling the AltStat register
wATACB2Signature. Only command blocks that have a valid
wATACB2Signature are interpreted as ATACB2 commands.
All other fields of the CBW and restrictions on the CBWCB
shall remain as defined in the USB Mass Storage Class Bulk-
Only Transport Specification. The ATACB2 must be 16 bytes
in length. The following table and text defines the fields of the
ATACB2.
Field Description
CY7C68310
Page 10 of 34