CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 32

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CY7C68310

Manufacturer Part Number
CY7C68310
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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14.0
15.0
The CY7C68310 contains high-speed analog circuitry that is
sensitive to system noise. In particular, noise on both analog
and digital power supplies must be minimized to ensure
reliable, high-performance operation. Special attention should
also be given to the design of the frequency generation,
voltage reference, and USB interface circuits. Cypress recom-
mends using the following guidelines in designing any product
that uses the CY7C68310.
Document 38-08030 Rev. *H
• The 3.3V power rail must remain above the 2.5V rail at all
• DP and DM trace lengths should be kept to within 2 mm of
• Maintain a solid ground plane under the DP and DM traces.
• Do not place vias on the DP or DM traces.
• All termination and pull-up resistors (including DP and DM) should be placed within 5 mm of the CY7C68310 pins.
• The crystal and RREF external resistor components should be placed as near the CY7C68310 pins as possible.
times for proper device operation.
each other and must not exceed 37 mm in total length, with
a preferred length of 20–30 mm.
Do not allow the plane to be split under these traces.
Package Diagram
PCB Layout Recommendations
80-lead Thin Plastic Quad Flat Pack (12 x 12 x 1.0 mm) A8012x12
Figure 14-1. 80-pin TQFP Package Diagram
• Isolate the DP and DM traces from all other signal traces
• The DP and DM common mode trace impedance should be
• The VDD power plane should be as solid as possible with
• Analog and digital power planes must be isolated using in-
• Ceramic or tantalum capacitors are required. Do not use
• Adequate bypass capacitance must be implemented very
by no less than 10 mm.
controlled to 45Ω with total differential impedance controlled
to 90Ω (±10%).
direct paths from the voltage regulator to all discrete com-
ponents. A four layer board is required with inner layers
dedicated to power and ground planes. Digital ground
should cover one entire layer of the design.
ductors.
electrolytic capacitors. Electrolytic capacitors have higher
lead inductance and series resistance values that have
been observed to contribute to increased power supply
noise.
near to the CY7C68310 power pins. One ceramic bypass
capacitor per power/ground pair is recommended.
CY7C68310
51-85175-**
Page 32 of 34

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