CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 18

no-image

CY7C68310

Manufacturer Part Number
CY7C68310
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68310-80AC
Manufacturer:
CYPRESS
Quantity:
1 831
Part Number:
CY7C68310-80AXC
Quantity:
902
Part Number:
CY7C68310-80AXC
Manufacturer:
ST
0
Part Number:
CY7C68310-80AXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY7C68310-8AC
Manufacturer:
CYPRESS
Quantity:
1 831
Table 6-2. EEPROM Organization (continued)
Document 38-08030 Rev. *H
0x0D
0x0E
0x0F
Address
I
2
C
PIO Mode Selection
Skip Pin Reset
Reserved
SYSIRQ User-defined Bits
General Purpose IO
ATAPI IRQ Disable
Reserved
Int Reason Disable
HS Indicator Enable
Reserved
General Purpose IO Pin
Enable
Field Name
Bits (7:5)
PIO Mode Selection. The PIO mode reported back to the
device if the Override PIO Timing configuration bit is set.
mode 0
mode 1
mode 2
mode 3
mode 4
Bit (4)
Skip nATARST assertion. Setting this bit prevents the
CY7C68310 from asserting nATARST during initialization of
the ATA/ATAPI device. If this bit is set to ‘1’, SRST Enable
(address 0x09, bit 0) must also be set to ‘1’.
‘0’ = Allow nATARST assertion
‘1’ = Disable nATARST assertion
Bits (3:0) – must be set to ‘0’.
Bits (7:3)
SYSIRQ USER_DEF[4:0] bits.
The value of these bits will be returned to the host via the
USB interrupt pipe as stated in Section 4.3.6.
Bits(2:0)
GPIO[2:0] pin values.
When the GPIO pins are configured as outputs, writing to
these bits will set the logic value of the GPIO pins to ‘0’ or ‘1’.
Reading this address, regardless of whether the GPIO pins
are set to input or output, returns the logic value from the
GPIO pins.
Bit (7)
Disables the use of the ATAIRQ signal with ATAPI devices.
‘0’ = ATAIRQ use enabled
‘1’ = ATAIRQ use disabled
Bit (6) – must be set to ‘0’.
Bit (5)
Setting to a ‘1’ causes CY7C68310 to ignore the contents of
the interrupt reason register when talking to an ATAPI
device.
Bit (4)
Enables GPIO2_nHS pin to indicate the current operating
speed of the device (if output is enabled).
‘0’ = normal GPIO operation
‘1’ = high-speed indicator enable
Bit (3) – must be set to ‘1’.
Bits (2:0)
GPIO[2:0] high-Z control. These bits have precedence over
bit 4 of this byte.
‘0’ = Output enabled (GPIO pin is an output).
‘1’ = high-Z (GPIO pin is an input).
000
001
010
011
100
Field Description
Required
I
2
C Data
CY7C68310
Page 18 of 34
Example
I
2
C Data
0x90
0x00
0x07

Related parts for CY7C68310