CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 6

• Manufacturer Part Number: CY7C68310
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4-2. USB Interrupt Pipe Data Bitmap
4.3.7
DRVPWRVLD can be used with removable devices (such as
compact flash) to indicate that the media device is present. Pin
polarity and function enable are controlled by bits 4 and 2,
respectively, of EEPROM address 0x0B. When DRVPWRVLD
is deasserted, the CY7C68310 will remove the pull-up on D+
(causing the CY7C68310 to drop off the USB), suspend all
ATA state machine activity, drive all ATA interface signals to ‘0’
(assuming ATAEN = ‘1’), and enter into a low-power state. The
CY7C68310 will remain in this state until DRVPWRVLD is
asserted, at which time it will enable the D+ pull-up, allow
resume of ATA state machine activity, and begin to drive the
ATA interface pins (assuming ATAEN = ‘1’).
Document 38-08030 Rev. *H
7
DRVPWRVLD
6
USB Interrupt Data Byte 1
5
NAK Request
No
4
Return Interrupt Data
Set Int_Data = 0
USB Interrupt
Int_Data = 1?
3
Pipe Polled?
Yes
Yes
Figure 4-2. SYSIRQ Latching Algorithm
2
1
No
0
4.3.8
The ATAEN pin allows ATA bus sharing with other host
devices. Deasserting ATAEN causes the CY7C68310 to high-
Z all ATA bus interface pins and suspend ATA state machine
activity, otherwise leaving the CY7C68310 operational (USB
operation
CY7C68310 to reset the drive and resume normal operation.
To disable USB operation and the ATA interface, the
DRVPWRVLD signal can be used in conjunction with ATAEN
to force the CY7C68310 into a low-power state until normal
operation is resumed. Note that disabling the ATA bus with the
ATAEN pin during the middle of a data transfer will result in
7
6
ATAEN
Yes
continues).
USB Interrupt Data Byte 0
5
No
Latch State of IO Pins
4
Asserting
Set Int_Data = 1
SYSIRQ=1?
Int_Data = 0
SYSIRQ=0?
Yes
and
3
ATAEN
2
CY7C68310
No
causes
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0
the