PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 35

• Manufacturer Part Number: PCF8523
• Description: Real-Time Clock (RTC) and calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8523
Product data sheet
At the end of every countdown, the timer sets the countdown timer flag CTAF (register
Control_2). CTAF may only be cleared by using the interface. Instructions, how to clear a
flag, is given in
When reading the timer, the current countdown value is returned and not the initial
value n. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
If a new value of n is written before the end of the actual timer-period, this value will take
immediate effect. It is not recommended to change n without first disabling the counter by
setting TAC[1:0] = 00 (register Tmr_CLKOUT_ctrl). The update of n is asynchronous to
the timer clock. Therefore changing it on the fly could result in a corrupted value loaded
into the countdown counter. This can result in an undetermined countdown period for the
first period. The countdown value n will be correctly stored and correctly loaded on
subsequent timer-periods.
Loading the counter with 0 effectively stops the timer.
When starting the countdown timer for the first time, only the first period will not have a
fixed duration. The amount of inaccuracy for the first timer-period, depends on the chosen
source clock, see
Table 39.
The generation of interrupts from the countdown timer is controlled via the CTAIE bit
(register Control_2).
Timer source clock
4.096 kHz
64 Hz
1 Hz
1
1
Fig 19. General countdown timer behavior


60
3600
countdown value, n
countdown counter
Hz
timer source clock
Hz
WD/CD [1:0]
In this example it is assumed that the countdown timer flag (CTAF) is cleared before the next
countdown period expires and that interrupt output is set to pulse mode.
First period delay for timer counter value n
CTAF
INT1
Section
All information provided in this document is subject to legal disclaimers.
Table
XX
XX
00
Rev. 3 — 30 March 2011
03
03
8.7.5.
39.
Minimum timer-period
n
n
(n  1) +
(n  1) +
(n  1) +
01
1
1
1



64
64
64
02
Hz
Hz
Hz
duration of first timer period after
enable may range from n−1 to n+1
01
Real-Time Clock (RTC) and calendar
03
02
n
Maximum timer-period
n + 1
n + 1
n +
n +
n +
01
1
1
1



64
64
64
Hz
Hz
Hz
03
PCF8523
© NXP B.V. 2011. All rights reserved.
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