PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 45

• Manufacturer Part Number: PCF8523
• Description: Real-Time Clock (RTC) and calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8523
Product data sheet
Fig 32. Bus protocol for read mode
S
S
8.11.5 I
1
1
0
0
slave address
slave address
1
1
One I
slave address byte is shown in
Table 44.
After a start condition, a valid hardware address has to be sent to a PCF8523 device.
The R/W bit defines the direction of the following single or multiple byte data transfer. For
the format and the timing of the START condition (S), the STOP condition (P) and the
acknowledge bit (A) refer to the I
is terminated by sending either a STOP condition or the START condition of the next data
transfer.
Bit
2
Fig 31. Bus protocol for write mode
C-bus protocol
0
0
S
2
0
0
C-bus slave address (1101000) is reserved for the PCF8523. The entire I
1
0
0
Slave address
7
MSB
1
1
I
2
C slave address byte
slave address
1
1
0
write bit
read bit
All information provided in this document is subject to legal disclaimers.
from PCF8523
from PCF8523
acknowledge
acknowledge
0
1
1
6
1
A
A
0
Rev. 3 — 30 March 2011
0
0 to n data bytes
register address
DATA BYTE
00h to 13h
0
write bit
5
0
from PCF8523
Table
acknowledge
0
2
C-bus characteristics. In the write mode, a data transfer
A
44.
from PCF8523
acknowledge
acknowledge
from master
4
1
register address
A
A
00h to 13h
STOP
P
LAST DATA BYTE
3
0
Real-Time Clock (RTC) and calendar
from PCF8523
acknowledge
A
no acknowledge
2
0
A
data bytes
0 to n
P
1
0
PCF8523
© NXP B.V. 2011. All rights reserved.
read register
data
set register
address
from PCF8523
acknowledge
013aaa339
A
2
0
LSB
R/W
C-bus
START/
013aaa338
STOP
P/S
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