M48T08-150PC1TR STMICROELECTRONICS [STMicroelectronics], M48T08-150PC1TR Datasheet - Page 14

• Manufacturer Part Number: M48T08-150PC1TR
• Description: CMOS 8K x 8 TIMEKEEPER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48T08, M48T08Y, M48T18
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit (ST) is the MSB of the seconds register. Setting
it to a '1' stops the oscillator. The M48T08/18/08Y
(in the PCDIP28 package) is shipped from STMi-
croelectronics with the STOP Bit set to a '1.' When
reset to a '0,' the M48T08/18/08Y oscillator starts
within one second.
Note: To guarantee oscillator start-up after initial
power-up, first write the STOP Bit (ST) to '1,' then
reset to '0.'
Calibrating the Clock
The M48T08/18/08Y is driven by a quartz-con-
trolled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate
within 1 minute per month at 25°C without calibra-
tion. The devices are tested not to exceed ± 35
ppm (parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T08/18/08Y improves to
better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature.
quency error that can be expected at various tem-
peratures. Most clock chips compensate for
crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T08/18/
08Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256
11., page
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration Byte
found in the Control Register. Adding counts
speeds the clock up, subtracting counts slows the
clock down.
The Calibration Byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is the Sign Bit; '1' indicates pos-
itive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The
first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
14/27
15. The number of times pulses are
Figure 10., page 15
stage, as shown in
shows the fre-
Figure
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration Byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T08/18/08Y may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration Byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of
standard test equipment. When the Frequency
Test (FT) Bit, the seventh-most significant bit in
the Day Register, is set to a '1,' and the oscillator
is running at 32,768 Hz, the LSB (DQ0) of the Sec-
onds Register will toggle at 512 Hz. Any deviation
from 512 Hz indicates the degree and direction of
oscillator frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would in-
dicate a +20 ppm oscillator frequency error, requir-
ing a –10 (WR001010) to be loaded into the
Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency. The device must be selected and ad-
dresses must be stable at Address 1FF9h when
reading the 512 Hz on DQ0.
The LSB of the Seconds Register is monitored by
holding the M48T08/18/08Y in an extended READ
of the Seconds Register, but without having the
READ Bit set. The FT Bit MUST be reset to '0' for
normal clock operations to resume.
For more information on calibration, see the Appli-
cation Note AN934, “TIMEKEEPER
®
Calibration.”