M48T08-150PC1TR STMICROELECTRONICS [STMicroelectronics], M48T08-150PC1TR Datasheet - Page 6

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M48T08-150PC1TR

Manufacturer Part Number
M48T08-150PC1TR
Description
CMOS 8K x 8 TIMEKEEPER SRAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
M48T08, M48T08Y, M48T18
OPERATION MODES
As
ray and the quartz-controlled clock oscillator of the
M48T08/18/08Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
Table 2. Operating Modes
Note: X = V
6/27
Deselect
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
Figure 6., page 5
1. See
IH
Table 11., page 20
or V
V
SO
IL
; V
4.75 to 5.5V
4.5 to 5.5V
to V
SO
V
V
= Battery Back-up Switchover Voltage.
PFD
or
SO
CC
shows, the static memory ar-
(1)
(min)
for details.
(1)
V
V
V
V
E1
X
X
X
IH
IL
IL
IL
V
V
V
V
E2
X
X
X
IH
IH
IH
IL
V
V
cells. The M48T08/18/08Y includes a clock control
circuit which updates the clock bytes with current
information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T08/18/08Y also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When V
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below the Battery Back-up Switchover Voltage
(V
which maintains data and clock operation until val-
id power returns.
G
X
X
X
X
X
IH
IL
SO
), the control circuitry connects the battery
V
V
V
W
X
X
X
X
IH
IH
IL
DQ0-DQ7
CC
High Z
High Z
High Z
High Z
High Z
D
D
OUT
IN
is out of tolerance, the circuit
Battery Back-up Mode
CMOS Standby
CC
Standby
Standby
Power
Active
Active
Active
. As V
CC
falls

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